• Sr. Physical Design Engineer , Annapurna…

    Amazon (Austin, TX)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and ... for physical design closure - Drive IO/Core block physical implementation through synthesis , floor planning, bus /...MS + 6yrs in EE/CS - 6+ years in ASIC Physical Design from - RTL-to-GDSII in either 7nm,… more
    Amazon (09/02/25)
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  • Digital Design Engineer

    Meta (Austin, TX)
    **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design ... virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more
    Meta (08/11/25)
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  • Physical Design Methodology Engineer

    Amazon (Austin, TX)
    …tool decisions. - Experience in high-performance, low-power physical design, and implementation techniques with industry standard synthesis , PnR, or Signoff ... our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud...years in developing design methodology or CAD flows in synthesis , PNR, or sign-off areas for advanced technology nodes.… more
    Amazon (09/02/25)
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  • SoC Physical Design Engineer

    Meta (Austin, TX)
    …requirements needed for our wearable products. **Required Skills:** SoC Physical Design Engineer Responsibilities: 1. Physical design implementation from RTL to ... architecture, to firmware, and algorithms.As an SoC Physical Design Engineer at Meta Reality Labs, you will perform physical...at Meta Reality Labs, you will perform physical design implementation of complex SoC and IP-subsystems. In this high… more
    Meta (07/22/25)
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  • Micro-Architect/Logic Designer (Memory Controller)

    Samsung Electronics Co., Ltd. (Austin, TX)
    …understanding of ASIC design flow including RTL design, verification, logic synthesis , timing analysis & ECO + Knowledge of JEDEC memory standards preferred + ... interact with the system architects, verification, performance/power and design implementation teams. You will be own and drive the...logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for… more
    Samsung Electronics Co., Ltd. (08/28/25)
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