• Principal Software Engineer

    Microsoft Corporation (Mountain View, CA)
    …Cloud" mission. From cloud game streaming to data services, the hardware we design is contributing to the success of millions of customers. The SCHIE team ... customers. This role will give you an opportunity to design and architect the systems and servers of tomorrow...hardware interfaces and define flows for boot flows of ASIC . + You will be responsible for firmware level… more
    Microsoft Corporation (08/08/25)
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  • Senior Mechanical Engineering Technical Leader

    Cisco (San Jose, CA)
    …are the Service Provider (SP) Mechanical and Thermal team responsible for the design of Cisco's best high-performance, provider class routers, the Cisco 8000 series. ... The Cisco 8000 series utilizes Cisco's revolutionary Silicon One ASIC that delivers unmatched performance and density with feature-rich functionality. We are… more
    Cisco (07/22/25)
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  • Sr. RFIC Layout Designer (Silicon Engineering)

    SpaceX (Sunnyvale, CA)
    …who will work alongside world-class cross-disciplinary teams (systems architecture, ASIC design , firmware, pre-silicon verification, post-silicon validation, ... satellite constellation and is providing fast, reliable internet to 6M+ users worldwide. We design , build, test, and operate all parts of the system - thousands of… more
    SpaceX (06/19/25)
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  • Principal Catheter NPI R&D Engineer, (San Diego,…

    Philips (San Diego, CA)
    …strong individual contributor on a cross-functional team responsible for the design and development of our next generation Intravascular Ultrasound Cardiac ... to the strategic direction and provide technical insights by actively participating in the design , prototyping, test method and test flow development, as well as in … more
    Philips (05/23/25)
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  • CPU Power Analysis Lead

    Qualcomm (Santa Clara, CA)
    …on RTL and Netlist using tools like Joules and PTPX. + Work closely with RTL design , Synthesis, and physical design teams to measure and optimize power. + ... propose new power optimization techniques at RTL, Synthesis and Physical Design Stages. + Tabulate metrics results...Power analysis and optimization required + 15+ years of ASIC design , or related work experience. +… more
    Qualcomm (07/16/25)
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  • Embedded Software Engineer (L1/L2)

    Cisco (San Jose, CA)
    …will write functional and design specs independently and work closely with HW, ASIC team to bring up new platforms. You will also collaborate and work with QA ... 3rd party ASICs, FPGAs, and SDK. Help to define, design and deliver new platforms for the next generation...of networking concepts and protocols * Demonstrated expertise in physical layer bring-up and debug processes * Excellent problem-solving… more
    Cisco (07/10/25)
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  • RFIC Engineer (Starshield)

    SpaceX (Hawthorne, CA)
    …problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace. RESPONSIBILITIES: + Design ... GaAs, GaN, or CMOS processes + Work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains + Perform IC… more
    SpaceX (07/24/25)
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  • Functional Verification Applications Engineer…

    Siemens (Fremont, CA)
    …and more cost-effectively. Our innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip ... design . We have a unique company culture. With its...and debugging skillsDeep knowledge of semiconductor IC industry - ASIC , SoC, Memory, Interconnect, CPU architectures, embedded systemsAbility to… more
    Siemens (05/17/25)
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  • Sr. CPU Architect, Project Kuiper

    Amazon (San Diego, CA)
    …teams to realize the architecture. - Contribute to the SoC floor planning and physical design effort. - Assist with SoC debug and bring-up. About the ... a growing Silicon development organization within Project Kuiper. We provide custom ASIC solution to enable Project Kuiper to provide connectivity and performance to… more
    Amazon (07/23/25)
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  • Senior Timing and Constraints Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …crossing of clock domains across hierarchical boundaries). + Collaborate with RTL, physical design , and verification teams to drive consistency and correctness ... experience) in Electrical or Computer Engineering with 4+ years' experience in ASIC Design and Timing. + Expertise in Primetime and timing constraints +… more
    NVIDIA (05/29/25)
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