- The Boeing Company (El Segundo, CA)
- …us. Boeing Electronic Products is seeking a talented and highly motivated ** ASIC /FPGA Design Engineering Manager** to develop state-of-the-art FPGAs/ASICs and ... of the Boeing product line - approximately half our design work is within the Space Intelligence & Weapons...at Boeing. **Position Responsibilities:** + Manage a portfolio of ASIC /FPGA development programs, typically two to four within a… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Amazon (Sunnyvale, CA)
- …as architecture, front end design , pre-silicon verification, FPGA prototyping, Emulation, Physical design , BROM, FW, substrate and package design , ... ASIC /SOC leads) to create project execution plans for ASIC /SOC development considering all criteria to design ...from architecture definition, RTL design , Verification, IP design , Physical design , silicon bring… more
- Palo Alto Networks (Santa Clara, CA)
- …military experience required - MSEE preferred + Minimum 5 years experience in ASIC design verification + Demonstrated success in taking multiple ASIC ... relationships, and the kind of precision that drives great outcomes. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the… more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... **Sr. ASIC Engineer** The application window is expected to...refining design and timing constraints for seamless physical design closure. As part of this… more
- Meta (Sunnyvale, CA)
- …Responsibilities: 1. Front End implementation flow development and support 2. Physical Design implementation flow development and support 3. RTL2GDS ... 4. Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory… more
- Meta (Sunnyvale, CA)
- …4. Power estimation and optimization strategies for all layers of abstraction in silicon design , from architecture to physical design . 5. Develop power ... optimization strategies for all layers of abstraction in silicon design , from architecture to physical design...code using Verilog/SystemVerilog or VHDL 16. Mathematical modeling of ASIC physical feature phenomenon 17. Frontend power… more
- NVIDIA (Santa Clara, CA)
- …closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and develop ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation,… more
- NVIDIA (Santa Clara, CA)
- …modules. What you'll be doing: + Be an integral part of the System ASIC Design team to help with the Micro-architecture definition for system-level functions, ... functions like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design...CHI + Familiar with OCP secure boot specification and physical security handling process + Possess design … more
- NVIDIA (Santa Clara, CA)
- …closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and develop ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation,… more