- Palo Alto Networks (Santa Clara, CA)
- …military experience required - MSEE preferred + Minimum 5 years experience in ASIC design verification + Demonstrated success in taking multiple ASIC ... relationships, and the kind of precision that drives great outcomes. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the… more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... **Sr. ASIC Engineer** The application window is expected to...refining design and timing constraints for seamless physical design closure. As part of this… more
- Meta (Sunnyvale, CA)
- …Responsibilities: 1. Front End implementation flow development and support 2. Physical Design implementation flow development and support 3. RTL2GDS ... 4. Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory… more
- Meta (Sunnyvale, CA)
- …4. Power estimation and optimization strategies for all layers of abstraction in silicon design , from architecture to physical design . 5. Develop power ... optimization strategies for all layers of abstraction in silicon design , from architecture to physical design...code using Verilog/SystemVerilog or VHDL 16. Mathematical modeling of ASIC physical feature phenomenon 17. Frontend power… more
- NVIDIA (Santa Clara, CA)
- …modules. What you'll be doing: + Be an integral part of the System ASIC Design team to help with the Micro-architecture definition for system-level functions, ... functions like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design...CHI + Familiar with OCP secure boot specification and physical security handling process + Possess design … more
- NVIDIA (Santa Clara, CA)
- …closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and develop ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation,… more
- NVIDIA (Santa Clara, CA)
- …closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and develop ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation,… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA, you'll join a group of hardworking ... . + Collaborate with architects, verification engineers, formal engineers, physical design engineers, and software engineers to...high bandwidth data paths. + A deep understanding of ASIC design flows including RTL design… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... , Verilog and/or System-Verilog with a deep understanding of physical design and VLSI + Experience with...+ Strong familiarity and experience with all stages of ASIC design flow including front end … more
- Palo Alto Networks (Santa Clara, CA)
- …precision that drives great outcomes. **Your Career** As a Systems Administrator in the ASIC / FPGA team you will interface with engineering teams regularly to help ... and maintain a world-class semiconductor development environment. You will work with multiple ASIC and FPGA engineering teams as well as IT and Infosec to build… more