- NVIDIA (Santa Clara, CA)
- NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of NVIDIA Networking chips. We're ... role requires working with multiple teams as Architecture, IP, Physical design , Timing and Post-Si teams. Complexity...design next generation clock topologies and modules. + ASIC Clock scheme definition. + Improve Power, Performance, and… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback **Minimum ... in SOC Design Integration and Front-End Implementation 18. Knowledge of Physical Design flow such as Floorplanning, CTS, Routing 19. Understanding of… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback **Minimum ... 12. Knowledge of SOC Integration (Clocking, Reset, PLL, etc) 13. Knowledge of front-end ASIC flows 14. Experience with RTL design using SystemVerilog or other… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback **Minimum ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....DFT Modes 3. Perform STA for full chip and Physical partition blocks using PrimeTime 4. Run Logic/ Physical… more
- NVIDIA (Santa Clara, CA)
- …you will own RTL synthesis and gate level optimization tasks + Collaboration with physical design to address timing, area, congestion tradeoffs + Drive timing ... as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology....generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing… more
- Cisco (San Jose, CA)
- …joining our **Cisco Silicon One** team which is the center of Cisco's SW and ASIC design , driving our game changing next generation network devices - Cisco ... Master Scheduler - ASIC , Silicon One Apply (https://jobs.cisco.com/jobs/Login?projectId=1443017) + Location:San Jose,...power how humans and technology work together across the physical and digital worlds. These solutions provide customers with… more
- Amazon (Sunnyvale, CA)
- …Verification LEC DRC LVS etc. - Be single point contact for bugs and issues for physical design team - Build flow in TCL, Python to ensure quality and faster ... infrastructure - 7+ years of silicon EDA and/or digital ASIC design experience Preferred Qualifications - Master's...IC Compiler, Fusion Compiler, Cadence synthesis APR tool - Physical aspect of VLSI designs - Strong written and… more
- Cisco (San Jose, CA)
- …or Master's degree on Electrical Engineering with at least 10 years of experience on ASIC chip design + Prior experience with RTL development on Asynchronous ... ASIC Engineering Technical Leader Apply (https://jobs.cisco.com/jobs/Login?projectId=1438623) + Location:San...for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers… more
- Broadcom (San Jose, CA)
- …and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks. + Participate in large complex design ... Sign-In before you apply.** **Job Description:** **Job Description:** + ASIC implementation engineer with demonstrated expertise in multiple disciplines including… more
- NVIDIA (Santa Clara, CA)
- …performance designs + Expertise in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication skills + Background in ... We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power...Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our next-generation mobile,… more