- Amazon (Cupertino, CA)
- …Develop and execute design automation mechanisms and flows. * Work with physical design teams to achieve performance and area requirements. Mentorship & ... Annapurna Labs we are at the forefront of hardware co- design not just in Amazon Web Services (AWS) but...while also being deeply important to our customers. We design and build every component of our hardware and… more
- Amazon (Sunnyvale, CA)
- …party IP blocks -Estimate power, performance, and area for significant IPs early in design cycle -Execute on design specifications to deliver high quality RTL ... that have gone to volume production -Hands on experience in low power design techniques -Strong written and verbal skills Preferred Qualifications -Master's or Ph.D… more
- NVIDIA (Santa Clara, CA)
- …or Computer Engineering or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis ... generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing...of multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg… more
- NVIDIA (Santa Clara, CA)
- …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the crowd: + Familiarity… more
- NVIDIA (Santa Clara, CA)
- …member of this team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to ... movement and low power design . + Familiarity with Verilog and ASIC design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 8 years of experience in DFT or physical design . + Experience with scan insertion, Automatic Test Pattern Generation ... JTAG (IJTAG) tools and flow. + Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc. **Preferred qualifications:** +… more
- Meta (Sunnyvale, CA)
- …11. Experience in SoC integration and ASIC architecture 12. Knowledge of Physical Design and Low power implementation 13. Experience with Machine learning ... through architecture, firmware, and algorithms.We are growing our Machine Learning ASIC Design and uArchitecture team within RL and are seeking engineers at… more
- Meta (Sunnyvale, CA)
- …considering Input/Output Physical Layer (IO PHY), SI/PI and physical design **Minimum Qualifications:** Minimum Qualifications: 13. Bachelor's degree ... with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors 17. Perform … more
- NVIDIA (Santa Clara, CA)
- …Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, Product teams and Physical Design teams to ... movement and low power design . + Familiarity with Verilog and ASIC design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL… more
- Arrow Electronics (Santa Clara, CA)
- **Position:** Physical Design Engineer (eInfochips Inc) **Job...by a minimum of 8 years of experience in ASIC or a related field, or a master's degree ... Description:** **Position: Sr. Physical Design Engineer (eInfochips Inc)** **Location: USA (Remote)** **Experience:** 10+...engineering with at least 8 years of experience in ASIC or related discipline. + Proficiency in Cadence tools… more