- Broadcom (San Jose, CA)
- …guidelines **Knowledge and Experience required:** + A good understanding of IP & ASIC design methodologies + Extensive experience with EDA DRC/LVS support + ... ease of use is critical. **Responsibilities:** Develop and support design automation flows for ASIC products and... products and associated IPs. This role involves + Physical verification runset support and development + Providing guidance… more
- Google (Sunnyvale, CA)
- SoC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more junior ... equivalent practical experience. + 4 years of experience with physical design . + Experience in physical...complex SoC. + Experience with multiple-cycles of SoC in ASIC design . + Experience with scripting languages… more
- Broadcom (San Jose, CA)
- …debugging, code and functional coverage + Floor plan, timing, congestion resolution with Physical Design team + Post silicon bring-up, debug, failure analysis. ... Group at Broadcom has brought some of the most complex and cutting edge networking ASIC 's and multi-chip solutions to market. The group develops ASIC 's for L2/L3… more
- Arrow Electronics (Santa Clara, CA)
- … ASIC Design and Development: + Design , implement, and verify ASIC components with a focus on PCIe physical layer requirements. + Utilize Verilog and ... experience in PCIe system architecture, with an emphasis on physical layer design and specification. + Ensure compliance with PCIe specifications, including… more
- Meta (Sunnyvale, CA)
- …2. Deliver quality RTL in collaboration with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs 4. Develop system tests in C ... **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon...ASIC architecture 10. Skilled in micro-architecture, RTL coding, design verification and SoC Integration of complex IPs 11.… more
- Texas Instruments (Santa Clara, CA)
- …+ A thorough understanding of digital logic design + Strong understanding of ASIC design flow from RTL to GDSII. + Familiarity with the Verilog language ... years or MSEE with 10 years of digital/mixed signal ASIC architecture/ design experience + Successfully taped out...+ Knowledge of MATLAB + Knowledge or experience with physical design flow + Strong time management… more
- Capgemini (San Francisco, CA)
- …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. + Minimum of 5 years in Sales Pursuit Management. ... foundries, EDA companies, and IP providers. + Background in ASIC Design or Semiconductor Technology R&D is...digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of… more
- Broadcom (San Jose, CA)
- …and dynamic environment. + Hands on experience with timing analysis and place and route tools for ASIC / SoC Design is a must. + Should have worked on tape out of ... before you apply.** **Job Description:** Candidate would be required to work on Design Implementation activities related to place and route and/ or timing closure -… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and documenting all phases of work. Skill Requirements: + Understanding of ASIC design flow. Good knowledge of physical design automation flow, Tcl or ... to make an impact on the world of technology. + Detailed understanding of physical design automation flow and EDA tool functions. + Running EDA tools in each… more
- Silvus Technologies (Los Angeles, CA)
- …presentation skills. + Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS + Office environment. ... fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer- Signal Processing_** who will report to the _Director of FPGA… more