- SpaceX (Sunnyvale, CA)
- …in scan insertion or DFT setup PREFERRED SKILLS AND EXPERIENCE: + Understanding of ASIC design flow, methodologies, physical design , and verification ... ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale,...design readiness for scan insertion through RTL and physical design Scan Design Rule… more
- Cisco (San Jose, CA)
- ASIC Design Technical Leader - Design ...in refining design and timing constraints for seamless physical design closure. As part of this team, ... provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco... team who oversees fullchip SDCs and works with physical design and DFT teams to close… more
- SpaceX (Sunnyvale, CA)
- …work extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your ... Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale,...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering and ASIC implementation).… more
- NVIDIA (Santa Clara, CA)
- …you will own RTL synthesis and gate level optimization tasks + Collaboration with physical design to address timing, area, congestion tradeoffs + Drive timing ... as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology....generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic… more
- Meta (Sunnyvale, CA)
- …Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/ physical synthesis using advanced ... Power, Performance, and Area 17. 2. Floor Planning and Placement 18. 3. Physical Design Execution for Clock Tree Synthesis and Routing optimization 19. 4 Static… more
- NVIDIA (Santa Clara, CA)
- …or Computer Engineering or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis ... generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic...of multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg… more
- Amazon (Cupertino, CA)
- …Develop and execute design automation mechanisms and flows. * Work with physical design teams to achieve performance and area requirements. Mentorship & ... Annapurna Labs we are at the forefront of hardware co- design not just in Amazon Web Services (AWS) but...while also being deeply important to our customers. We design and build every component of our hardware and… more
- Amazon (Sunnyvale, CA)
- …party IP blocks -Estimate power, performance, and area for significant IPs early in design cycle -Execute on design specifications to deliver high quality RTL ... that have gone to volume production -Hands on experience in low power design techniques -Strong written and verbal skills Preferred Qualifications -Master's or Ph.D… more
- NVIDIA (Santa Clara, CA)
- …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the crowd: + Familiarity… more
- Google (Sunnyvale, CA)
- …evaluations of vendors, provide recommendations and employ best practices. Your work will streamline ASIC physical design workflows, make our team of ... Physical Design Flow and Methodology Engineer _corporate_fare_... ASIC tapeouts. You will work with industry-standard physical design EDA tools and RTL To… more