• ASIC Physical Design

    Cisco (San Jose, CA)
    …most complex ASICs being developed in the industry. Your Impact You'll be joining our Physical Design team at Cisco Silicon One group, which is responsible for ... or equivalent similar experience. * 10+ years of experience in Physical Design . * Experience working on Fullchip activities. * Experience with RTL2GDSII… more
    Cisco (05/02/25)
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  • ASIC FPGA Design and Verification…

    The Boeing Company (Mountain View, CA)
    …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers** (Experienced, Lead, or… more
    The Boeing Company (05/24/25)
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  • ASIC Design Technical Leader…

    Cisco (San Jose, CA)
    ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...refining design and timing constraints for seamless physical design closure. As part of this… more
    Cisco (05/02/25)
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  • Principal Engineer, ASIC Design

    Palo Alto Networks (Santa Clara, CA)
    …meet aggressive goals for area, timing, power, and testability in close collaboration with ASIC physical design engineers + Perform synthesis + Optimize ... military experience required + Minimum 8 years experience in ASIC design + Demonstrated success in taking...+ Debugging simulation, emulation, and silicon validation + Analyzing physical design reports and fixing timing and… more
    Palo Alto Networks (05/17/25)
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  • ASIC Physical Design Lead

    Google (Sunnyvale, CA)
    technical field, or equivalent practical experience. + 8 years of experience in ASIC physical design and methodologies in advanced process nodes. + ... and its integration within AI/ML-driven systems. As an Application-Specific Integrated Circuit ( ASIC ) Physical Design Lead on the chip implementation… more
    Google (05/24/25)
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  • ASIC Engineering Technical Leader…

    Cisco (San Jose, CA)
    ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...refining design and timing constraints for seamless physical design closure. As part of this… more
    Cisco (05/10/25)
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  • Technologist, ASIC Development Engineering

    SanDisk (Milpitas, CA)
    …seamless integration of ASIC designs into larger systems + Conduct thorough design reviews and provide technical leadership to junior engineers + Analyze and ... development + Contribute to the development of best practices and methodologies for ASIC design within the organization + Optimize designs for power efficiency,… more
    SanDisk (04/12/25)
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  • ASIC /FPGA Design Senior Engineering…

    The Boeing Company (Mountain View, CA)
    …us. Boeing Electronic Products is seeking a talented and highly motivated ** ASIC /FPGA Design Senior Engineering Manager** to develop state-of-the-art digital ... the enterprise. This is an exciting time for the organization where we're onboarding design and verification engineers at every level at three new sites, and the new… more
    The Boeing Company (05/24/25)
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  • ASIC Engineering Manager, EDA…

    Meta (Sunnyvale, CA)
    …( ASIC Development tools, Compute/Storage/Licensing management,etc.) and/or CAD Methodology ( Physical Design , Timing Methodology, Physical Verification, ... and Enterprise Engineering teams on adapting FB infrastructure to ASIC design solutions, including but not limited...meet the needs of internal customers. 6. Partner with technical program management and supply chain team members to… more
    Meta (05/16/25)
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  • Sr Director, ASIC Engineering

    Palo Alto Networks (Santa Clara, CA)
    …for networking IP and backend + Technical expertise on the entire ASIC design flow-architecture, logic design , RTL coding, verification, FPGA validation, ... synthesis, DFT, timing closure and physical backend leading to tape-out + Education/Training - BSEE/MSEE...10+ year industrial experience + Minimum of 10 years ASIC design /verification and 5 years of … more
    Palo Alto Networks (05/13/25)
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