- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing,… more
- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic...with Static Timing Analysis (STA) + Experience physical design and optimization eg, synthesis, floorplanning,… more
- Cisco (San Jose, CA)
- …teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this ... startup-style team. You'll collaborate with exceptional talent with deep ASIC design and development expertise. As part...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing… more
- SpaceX (Irvine, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- The Boeing Company (Mountain View, CA)
- …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... & Weapons Systems has an exciting opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers**...team and third-party IP as needed + Perform static timing analysis, LEC, CDC, linting, and other necessary checks… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer, Physical Design Responsibilities:...cross-functional teams, IP, and EDA vendors 11. Experience in physical design and timing closure… more
- Meta (Sunnyvale, CA)
- **Summary:** Join Meta's Infrastructure organization to leverage your expertise in ASIC Physical Design , driving high-performance, AI/ML SoC and IP ... and innovation of our data center applications. **Required Skills:** ASIC Engineer Physical Design Responsibilities:...equivalent practical experience 10. 8+ years of experience in physical design and timing closure… more
- Teledyne (Goleta, CA)
- …Responsibilities:** + Flow down and documentation of customer requirements + Perform digital design , timing design , and detailed digital simulations + ... on a team that wins. **Job Description** **Job Summary:** ASIC Digital Design Engineer: Oversees definition, ...+ Clock/Power optimization for low-power ASICs. + Perform Back-End Physical Design as needed + Floorplanning and… more
- SpaceX (Sunnyvale, CA)
- Principal ASIC Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... ultimate goal of enabling human life on Mars. PRINCIPAL ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX...timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality… more
- Cisco (San Jose, CA)
- …teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this ... provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing… more