- Google (Sunnyvale, CA)
- Senior ASIC Physical Design Engineer...Experience working with external partners on Physical Design (PD) closure. + Experience in Static Timing ... including key stages like floorplanning, place and route, and timing closure). + Experience in Python, Tcl, or Perl...architecture and its integration within AI/ML-driven systems. As an ASIC Physical Design Engineer, you… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and ... logic synthesis, netlist quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing constraints generation… more
- Cisco (San Francisco, CA)
- … and verification, digital signal processing, memory and custom library development, physical design , DFT, signal integrity, and advanced packaging. Work with ... (eg, Python, Perl, TCL) for automation. + Familiarity with ASIC /SoC design flow including synthesis, place &... verification methodologies (eg, UVM, SystemVerilog) + Understanding of physical design and DFT ( Design … more
- NVIDIA (Santa Clara, CA)
- …is a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing analysis, floor planning, ECO, bringup ... NVIDIA is looking for a Senior ASIC Design Engineer to join our...Subsystem Design team, you will collaborate with architects/ design verification/formal verification/ physical design team… more
- NVIDIA (Santa Clara, CA)
- …CPU team, you'll be a liaison between Logic design and Physical design teams responsible for achieving timing , area, performance and power goals of the ... other related high-performance semiconductor designs. + Physical design expertise including hands-on synthesis experience, timing ...expertise is preferred as is a deep understanding of ASIC design flow including RTL design… more
- NVIDIA (Santa Clara, CA)
- … closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing… more
- NVIDIA (Santa Clara, CA)
- … closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing… more
- Palo Alto Networks (Santa Clara, CA)
- …scenarios, close coverage, and add design -for-debug features. + **Partner** with physical - design teams: review synthesis/ timing reports, rewrite RTL to ... CE, or CS (MSEE or equivalent military experience preferred). + 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production. + Solid… more
- NVIDIA (Santa Clara, CA)
- …modules. What you'll be doing: + Be an integral part of the System ASIC Design team to help with the Micro-architecture definition for system-level functions, ... controllers. + You will be responsible for the RTL design , logic synthesis, and timing analysis of...functions like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design… more
- NVIDIA (Santa Clara, CA)
- …+ A deep understanding of ASIC design flows including RTL design , verification, logic synthesis and timing analysis. + Strong interpersonal skills and an ... We are looking for a Senior ASIC Design Engineer to join our.... + Collaborate with architects, verification engineers, formal engineers, physical design engineers, and software engineers to… more
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