- Silvus Technologies (Irvine, CA)
- …using Verilog and System-Verilog. * Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or ... career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and… more
- Cisco (Milpitas, CA)
- …10+ years of experience with a Bachelors' degree. Experience expected to be in ASIC /FPGA design . + Experience in end-to-end FPGA development process. + Hands-on ... Impact** We are seeking a highly experienced and accomplished FPGA Senior Design Engineer to provide technical leadership and deep expertise in the architecture,… more
- Broadcom (Irvine, CA)
- … specifications from the marketing requirements and/or system requirements prepare detailed design document, timing constraint file RTL coding, Lint checks, CDC, ... This opening is for working on chips that enable Physical Layer Products for High Speed Optical Communication. architect...level simulations & silicon debug Scripting for various IC design tasks such as STA, equivalency checks, test bench,… more
- Broadcom (San Jose, CA)
- …academic standing. 2). Must have in-depth knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough ... 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static timing analysis. 6). Work directly with… more
- Microsoft Corporation (Mountain View, CA)
- …program you will be interacting with various teams, including architecture, verification, and physical design , ensuring that the design is implemented and ... engineers to help achieve that mission. We are looking for a **Senior Design Engineer** to work in the dynamic Microsoft Artificial Intelligence System on Chip… more
- Silvus Technologies (Irvine, CA)
- …+ Experience using MATLAB. + Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS + Office environment. + ... to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA/RTL Design Engineer_** who will report to the _Director of FPGA Engineering_ on the… more
- Silvus Technologies (Irvine, CA)
- …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
- NVIDIA (Santa Clara, CA)
- …products. + Domain & Technical Expertise: Deep knowledge in EDA/VLSI (eg, synthesis, physical design , verification, timing , reliability, or CAD algorithms) ... methods. + Apply deep learning and GPU computing to improve ASIC and VLSI design tool flows. + Collaborate cross-functionally with circuit design ,… more
- Cisco (Milpitas, CA)
- …5+ years of experience with a Bachelors' degree. Experience expected to be in ASIC /FPGA design . + Proficiency in end-to-end FPGA development process. + Hands-on ... We are looking for a skilled and proactive FPGA Design Engineer with 3+ years of industry experience to...large, resource-intensive blocks (eg, DSP pipelines, memory controllers). + Timing Closure: Independently apply and analyze timing … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design -for-Test (DFT), Place & Route and Static Timing Analysis (STA).You ... ideal for someone with several years of hands on ASIC /IC design experience who is looking for...tools Or Cadence or Synopsys place and route tools ( Physical Synthesis, PnR, CTS, Static Timing Analysis)… more
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