• Digital Design Engineer

    Meta (Sunnyvale, CA)
    Design Engineer Responsibilities: 1. Contribute to microarchitectural feature definition, RTL design , design verification and project planning 2. ... **Summary:** We are looking for a Digital Design Engineer to support our Reality...and ASIC architecture 10. Skilled in micro-architecture, RTL coding, design verification and SoC Integration… more
    Meta (09/09/25)
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  • Physical Design Flow and Methodology…

    Google (Sunnyvale, CA)
    Physical Design Flow and Methodology Engineer +...ASIC tapeouts. You will work with industry-standard physical design EDA tools and RTL To GDS ... in a semiconductor environment. + Experience developing automated physical design workflows from RTL to GDS, utilizing...recommendations and employ best practices. Your work will streamline ASIC physical design workflows, make our team… more
    Google (09/28/25)
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  • Principal Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …engineers to help achieve that mission. We are looking for a **Principal Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... + Own and drive the development of microarchitecture and RTL design , coding, and verification of complex...trade-offs, post-silicon debug, and successful delivery of IP and ASIC /SoC designs. + 7+ years of experience in high-speed… more
    Microsoft Corporation (09/30/25)
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  • Sr. Physical Design Engineer

    Amazon (Cupertino, CA)
    …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new ... Basic Qualifications - BS + 8yrs or MS + 6yrs in EE/CS - 6+ years in ASIC Physical Design from - RTL -to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm - Block … more
    Amazon (09/02/25)
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  • Sr. Physical Design Engineer

    Amazon (Cupertino, CA)
    …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new ... team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL...power, area analysis and trade-offs - Experience with modern ASIC /FPGA design and verification tools - Experience… more
    Amazon (10/02/25)
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  • Power Optimization Engineer - New College…

    NVIDIA (Santa Clara, CA)
    …GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design , methodology and AI based power optimization solutions. You ... We are now looking for a Power Optimization Engineer - New College Grad! NVIDIA prides in...will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design more
    NVIDIA (09/17/25)
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  • Senior Power Architecture and Optimization…

    NVIDIA (Santa Clara, CA)
    …of this team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study ... now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA prides ourselves in having energy efficient products....power design . + Familiarity with Verilog and ASIC design principles, including knowledge of Power… more
    NVIDIA (09/16/25)
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  • CAD Flow Development Engineer

    NVIDIA (Santa Clara, CA)
    …the world. Are you a computer engineer with a passion for automation of VLSI ASIC design ? Be part of a diverse team creating NVIDIA's chip design ... responsible for NVIDIA's front-end ASIC software including RTL synthesis, equivalence checking, and early physical design...design , formal equivalence checking. + Experience in other ASIC methodologies such as RTL Lint, CDC,… more
    NVIDIA (09/05/25)
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  • SoC Physical Design Engineer

    Meta (Sunnyvale, CA)
    …**Required Skills:** SoC Physical Design Engineer Responsibilities: 1. Physical design implementation from RTL to netlist for complex digital blocks or ... through architecture, to firmware, and algorithms.As an SoC Physical Design Engineer at Meta Reality Labs, you...routing, static timing analysis and signoff 2. Collaborate with RTL design , DFT, verification, and power teams… more
    Meta (08/01/25)
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  • Principal Design Engineer Manager…

    Microsoft Corporation (Mountain View, CA)
    …will manage and optimize the Cloud infrastructure. We are looking for a **Principal Design Engineer Manager - AI Network Silicon** to join the team. Microsoft's ... functions and features. + Be responsible for the logic design /Register Transfer Level ( RTL ) entry, design...Balancing, Traffic pattern, Uniform Latency) + Experience leading logic design teams + Multiple successful ASIC tape… more
    Microsoft Corporation (09/26/25)
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