- Broadcom (San Jose, CA)
- …line interfaces and protocols.. You will be responsible for the micro-architecture, design , RTL coding, debugging and synthesis of complex functional blocks ... leading network switch products. Responsibilities include: + High quality micro-architecture and design specifications + Verilog RTL coding and synthesis +… more
- NVIDIA (Santa Clara, CA)
- …GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design , methodology and AI based power optimization solutions. You ... We are now looking for a Power Optimization Engineer - New College Grad! NVIDIA prides in...will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design… more
- Google (Sunnyvale, CA)
- Physical Design Flow and Methodology Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... an emphasis on computer architecture. + 10 years of experience in physical design flow and methodologies for high-performance ASIC /SoC projects. + Experience in… more
- NVIDIA (Santa Clara, CA)
- …of this team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study ... now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA prides ourselves in having energy efficient products....power design . + Familiarity with Verilog and ASIC design principles, including knowledge of Power… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Scripts* Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San...opportunities* Run Verilog simulations to enable IP benchmarking* Run RTL synthesis for area and timing analysis* Present IP… more
- Amazon (Cupertino, CA)
- …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze ... Fine tune cloud infrastructure to improve compute and storage utilization for physical design work. Interface directly with RTL , Physical Design , Package… more
- Broadcom (San Jose, CA)
- … RTL verification methodologies including System Verilog. + Strong experience in ASIC design verification flows and DV methodologies + Strong working ... a Candidate Account, please Sign-In before you apply.** **Job Description:** The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and… more
- NVIDIA (Santa Clara, CA)
- …integrated logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design , verification, ... looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software solutions to… more
- Meta (San Diego, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... our industry leading virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block… more
- Silvus Technologies (Irvine, CA)
- …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
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