- NVIDIA (Santa Clara, CA)
- …of this team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study ... now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA prides ourselves in having energy efficient products....power design . + Familiarity with Verilog and ASIC design principles, including knowledge of Power… more
- NVIDIA (Santa Clara, CA)
- …GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design , methodology and AI based power optimization solutions. You ... are now looking for a Power Architecture and Optimization Engineer - New College Grad! NVIDIA prides in having...will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design… more
- SpaceX (Sunnyvale, CA)
- …analyzing results + Experience with scripting languages, eg Python for automation + RTL design , chip bring-up, and post-silicon validation experience + Ability ... Design Verification Engineer (Silicon Engineering) Sunnyvale,...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation). In… more
- Qualcomm (Santa Clara, CA)
- …multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design and physical design teams to identify timing ... in Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related work experience. OR Master's degree… more
- Amazon (Northridge, CA)
- …Create and release FPGAs through the development phases of uArchitecture- RTL Design -Physical Implementation-Timing Closure-Simulation Validation- Lab Based ... state of the art in distributed systems and hardware design . As an FPGA engineer on the...to customers - 3+ years of experience with modern ASIC / FPGA design and verification tools… more
- Qualcomm (Folsom, CA)
- … Design Timing Engineer , you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs ... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC,...Layout Parasitic Extraction, feed through handling, + Knowledge of ASIC back-end design flows and methods and… more
- NVIDIA (Santa Clara, CA)
- …integrated logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design , verification, ... looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software solutions to… more
- Qualcomm (San Diego, CA)
- …Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related work experience. OR ... and customers to solve the toughest issues spanning board design , SoC RTL , microcontroller firmware, OS/software, and...Science, Engineering, or related field and 3+ years of ASIC design , verification, validation, integration, or related… more
- Qualcomm (San Diego, CA)
- …Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design , verification, validation, integration, or related work experience. OR ... Science, Engineering, or related field and 7+ years of ASIC design , verification, validation, integration, or related...power use, and verification or similarly for custom circuit design /layout flow. + Utilizes tools/applications (eg, RTL … more
- Meta (Sunnyvale, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... our industry leading virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block… more