- Meta (Austin, TX)
- …PLL, etc) 13. Knowledge of front-end ASIC flows 14. Experience with RTL design using SystemVerilog or other HDL. 15. Experience with communicating across ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat… more
- Qualcomm (Austin, TX)
- …a closely related field is preferred + 5+ years of experience with ASIC design and verification tools, techniques, and methodology **Preferred Qualifications** + ... closely related field + 5+ years of experience with ASIC design and verification tools, techniques, and...and methodology + 5+ years of experience with digital design concepts and RTL languages such as… more
- Meta (Austin, TX)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer , you will be ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...scratch. 13. Experience debugging fails to the line of RTL , closing out bug fixes, using Verdi or equivalent… more
- Meta (Austin, TX)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Micro-architecture development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Qualcomm (Austin, TX)
- …Science, or a closely related field + 2+ years of experience with ASIC design and verification tools, techniques, and methodology **Preferred Qualifications** + ... closely related field + 3+ years of experience with ASIC design and verification tools, techniques, and...and methodology + 3+ years of experience with digital design concepts and RTL languages such as… more
- Meta (Austin, TX)
- …data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development. 2. RTL development using ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...one of these skills (minimum 3 years): Micro-architecture and RTL development for complex control and data path IPs,… more
- Meta (Austin, TX)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Micro-architecture development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Meta (Austin, TX)
- …Back End PD tools such as Fusion Compiler, Innovus 19. Experience with Understanding RTL design using SystemVerilog or other HDL. 20. Experience with EDA tools ... looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC...(SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1.… more
- Meta (Austin, TX)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Emulation Responsibilities: 1. Develop emulation testbenches in System ... **Summary:** Meta is hiring ASIC Emulation Engineers within our Infrastructure organization. We...and/or C/C++. 2. Deliver emulation and prototyping models from RTL on industry standard emulation and prototyping platforms. 3.… more
- Meta (Austin, TX)
- **Summary:** As an Networking ASIC Engineer on the Infrastructure silicon team at Meta, you will be a key player in defining the networking architecture for the ... with cross functional teams working on data center networking architecture, network system design , micro-architecture, RTL design , Design Verification,… more