• Principal Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …and drive the development of microarchitecture and RTL design, coding, and verification of complex IP blocks, including: + Mixed-signal IPs + High-speed interfaces ... DRC (Design Rule Checking) + Develop basic test benches. + Support verification , DFT (Design for Test), and post-silicon validation activities in collaboration with… more
    Microsoft Corporation (09/30/25)
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  • Sr. Silicon Validation Engineer, DVT Silicon Dev

    Amazon (San Diego, CA)
    …around the world. We are seeking a highly motivated and experienced Post-Silicon Verification Engineer with strong expertise in Digital ASIC and modem (PHY ... power, performance, and reliability. * Collaborate closely with design, RTL verification , firmware, and systems teams to root-cause and resolve silicon issues.… more
    Amazon (09/07/25)
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  • Digital FPGA Engineer Level 4 (AHT)

    Northrop Grumman (Los Angeles, CA)
    …and continuously drive innovation. The selected individual will work on FPGA and ASIC Design across the full product life cycle process. In this capacity, you ... electrical engineering or other STEM discipline with 8 years of digital verification engineering experience using industry standard simulation tools; 6 years with an… more
    Northrop Grumman (09/07/25)
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  • Senior GPU Architect

    NVIDIA (Santa Clara, CA)
    …binning strategy for our GPU product s + Define, build, and drive the verification test plan for the strategy above for specific GPU products to ensure outstanding ... refine a C++ library + Collaborate with multiple teams including Architecture, ASIC , DV, Emulation, and Infrastructure to achieve seamless integration and strictly… more
    NVIDIA (07/31/25)
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  • Hardware Simulator SDE I, AWS Machine Learning…

    Amazon (Cupertino, CA)
    …builds functional models of these ML accelerator chips to speed up SoC verification and system software development. We're looking for a Hardware Simulator SDE to ... testing, and debug - Work closely with architecture, RTL design, design verification , emulation, and software teams to build, debug, and deploy your models… more
    Amazon (10/02/25)
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  • Digital FPGA Engineer Level 3 (AHT)

    Northrop Grumman (Los Angeles, CA)
    …and continuously drive innovation. The selected individual will work on FPGA and ASIC Design across the full product life cycle process. In this capacity, you ... electrical engineering or other STEM discipline with 5 years of digital verification engineering experience using industry standard simulation tools; 3 years with an… more
    Northrop Grumman (10/02/25)
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  • VLSI CAD Engineer

    NVIDIA (Santa Clara, CA)
    …You will have the chance to create novel flows for circuit design and verification to help expedite chip development. What you will be doing: + Developing scalable ... around vendor EDA tools to streamline circuit design and verification workflows. + Support circuit design engineers to automate...and Monte Carlo simulations. + Previous work in VLSI, ASIC , or EDA is a definite plus. + Ability… more
    NVIDIA (10/01/25)
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  • Lead Electrical Engineer (L5)(IEC)

    L3Harris (Anaheim, CA)
    …description document, etc.) and flow down applicable requirements to other groups (software, ASIC , & test) so that they can contribute to realize the end solution ... plans. . Ability to develop circuit designs, requirements, design descriptions, verification plans/procedures, customer CDRLs to meet program schedules. . Ability to… more
    L3Harris (08/08/25)
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  • SOC Design - STA, Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …* Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. * Full chip timing constraints development, full chip / Sub-System STA and ... SoC timing signoff flow. * Work for Systems and Architecture, SoC Integration, Verification , DFT, Mixed Signal, IP owners, Synthesis, Place & Route and other… more
    Amazon (08/01/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    …of Computer Vision/Image Sensing IP. 2. Contribute to chip-level integration, verification plan development and verification . 3. Define timing constraints, ... 16. SystemVerilog OVM/UVM experience. 17. Experience in SoC integration and ASIC architecture. 18. Experience with low power design and optimization, including… more
    Meta (08/01/25)
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