- Qualcomm (Santa Clara, CA)
- …Engineering with 3+ years of practical experience + Strong fundamentals in digital ASIC design; experience using Verilog or VHDL + Experience with ASIC ... the Mentor Tessent tools + Experience with defining and implementing SOC level verification on large designs. + Experience in TCL, Perl/Python and Shell scripting… more
- Arrow Electronics (San Jose, CA)
- …+ Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical or Computer Engineering with ... 5+ years of ASIC or related experience. + Experience with **block/full chip...Spyglass CDC and glitch analysis + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with… more
- Amazon (Sunnyvale, CA)
- …Sub System level. - Drive block physical implementation through synthesis, formal verification , floor planning, bus / pin planning, place and route, power/clock ... distribution, congestion analysis, timing closure, IR drop analysis, physical verification , ECO and sign-off. - Work closely with third...Qualifications - BS in EE/CS - 7+ years in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such… more
- Microsoft Corporation (Mountain View, CA)
- …and drive the development of microarchitecture and RTL design, coding, and verification of complex IP blocks, including: + Mixed-signal IPs + High-speed interfaces ... DRC (Design Rule Checking) + Develop basic test benches. + Support verification , DFT (Design for Test), and post-silicon validation activities in collaboration with… more
- Amazon (San Diego, CA)
- …around the world. We are seeking a highly motivated and experienced Post-Silicon Verification Engineer with strong expertise in Digital ASIC and modem (PHY ... power, performance, and reliability. * Collaborate closely with design, RTL verification , firmware, and systems teams to root-cause and resolve silicon issues.… more
- Broadcom (San Jose, CA)
- …be responsible for leading most complex and cutting edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to ... implementation, verification , timing closure, ATE pattern bringup. . You will...and PHY/IO's + Scan flow development, ATPG pattern generation, verification and coverage analysis + Experience working with Mentor/Siemens… more
- NVIDIA (Santa Clara, CA)
- …binning strategy for our GPU product s + Define, build, and drive the verification test plan for the strategy above for specific GPU products to ensure outstanding ... refine a C++ library + Collaborate with multiple teams including Architecture, ASIC , DV, Emulation, and Infrastructure to achieve seamless integration and strictly… more
- Cisco (San Jose, CA)
- …**Your Impact:** You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... the testability features coordinated in the RTL. + Work closely with the design/design- verification and PD teams to enable the integration and validation of the Test… more
- Qualcomm (San Diego, CA)
- …Machine learning, IoT and Automotive. This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced ... detailed understanding of RTL design, synthesis, static timing analysis, formal verification , PLDRC, clock domain crossing, and low power techniques. Knowledge and… more
- NVIDIA (Santa Clara, CA)
- …and implementation, define the validation scope, develop the post-silicon verification infrastructure (Testplans, Tests, Scripts to analyze data), implement ... the design. + You will be working multi-functionally with ASIC , SW and System teams to accomplish your tasks....of meaningful validation experience. + Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools… more