• Senior Timing and Constraints Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …across hierarchical boundaries). + Collaborate with RTL, physical design, and verification teams to drive consistency and correctness across design stages. What ... equivalent experience) in Electrical or Computer Engineering with 4+ years' experience in ASIC Design and Timing. + Expertise in Primetime and timing constraints +… more
    NVIDIA (05/29/25)
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  • Principal Catheter NPI R&D Engineer, (San Diego,…

    Philips (San Diego, CA)
    …prototyping, test method and test flow development, as well as in design verification and validation processes. You support the team by sharing your knowledge and ... catheters, guidewires, balloons, stents). Experience with electromechanical products, including ASIC /transducer and ultrasound technology is highly desirable. + You… more
    Philips (05/23/25)
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