- Amazon (Cupertino, CA)
- …Verilog, and simulation/emulation platforms - Proven track record of leading successful ASIC verification projects from planning to tapeout - Strong analytical ... Basic Qualifications - 8+ years of hands-on experience in ASIC /VLSI design verification , with a strong understanding of verification methodologies… more
- NVIDIA (Santa Clara, CA)
- …cycles, this is your place to be. What you'll be doing: + Responsible for ASIC design verification for various processing blocks in a SOC. Work in key ... success in ASIC Development + Experience owning processing ASIC , IP or SoC design verification + Experience running and delivering complex mixed language UVM… more
- Google (Goleta, CA)
- …the quantum electronics team, providing key technical contributions in the area of ASIC Design Verification (DV) as we realize sophisticated electronics for ... and readout electronics. You will contribute to the entire verification lifecycle for our ASICs, collaborating with ASIC... verification lifecycle for our ASICs, collaborating with ASIC architects and digital designers to understand the chip… more
- Amazon (Sunnyvale, CA)
- …related discipline, or equivalent experience * 5+ years of experience in FPGA/ ASIC design verification * Experience planning, developing, and using constrained ... SystemVerilog/UVM * Experience developing and implementing test plans. * Experience with FPGA/ ASIC design and verification tools (Synopsys, Vivado, Quartus) *… more
- SpaceX (Irvine, CA)
- …phases of ASIC and/or FPGA design flow (eg synthesis, timing closure, verification ) + Work with ASIC backend/implementation teams as needed + Bring-up and ... FPGA/ ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply...the ultimate goal of enabling human life on Mars. FPGA/ ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- ManpowerGroup (Santa Clara, CA)
- …of UVM verification , DV tools & methodologies. + Deep technical background in ASIC & SOC verification . + Experience with Cadence or Synopsys Verification ... Our client, a leading technology firm, is seeking a Verification Engineer to join their team. As a Verification Engineer, you will be part of the design … more
- Qualcomm (San Diego, CA)
- …Systems Engineering, or related work experience. **Preferred Qualifications:** + 3 years ASIC design, verification , or related work experience + Verification ... skills: Formal verification (Static and Dynamic), Assertion based verification , FPV an DPV + Design debug, Deep bug hunting, + Formal test planning, Formal… more
- BAE Systems (San Diego, CA)
- …random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools (Mentor Questa or Cadence) + ... your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification environments.… more
- Two95 International Inc. (Sunnyvale, CA)
- …UVM and System Verilog Requirement:. * 5+ or more years of proven experience on ASIC / SoC / IP Verification . * Strong experience in SystemVerilog and UVM ... Hi, Title: Lead / Senior Verification engineer Location: San Jose, CA / Santa Clara, CA Duration: 6+ Months Rate: $Open Skills:… more
- Arrow Electronics (Mountain View, CA)
- … Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ASIC SoC and providing verification ... test FW and create test plan documentation to cover ASIC features. * Develop and debug SoC ASIC...specification documents * Implement and maintain integrated end-to-end formal verification flow for the formal verification objective.… more