- NVIDIA (Santa Clara, CA)
- …We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer ! Someone who ... CMOS technologies using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.… more
- Silvus Technologies (Irvine, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and work ... addressing challenging real-world communication needs. The Principal FPGA / RTL Design Engineer position will be based at Silvus' Irvine CA engineering facility… more
- Siemens (Fremont, CA)
- …ID: 459362 Employer: Siemens Industry Software Inc. Job Title: Consultant Application Engineer [MULTIPLE POSITIONS] Job Location: Fremont, CA Job Type: Full Time ... pre-sales, post-sales and technical support of Catapult High Level Synthesis, Verification and power optimization; assisting Account Managers to determine sales… more
- Silvus Technologies (Irvine, CA)
- …test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers. + Provide support to the ... (MSEE). + Basic MATLAB skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a guarantee. It is based on… more
- Qualcomm (San Diego, CA)
- …Machine learning, IoT and Automotive. This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced ... detailed understanding of RTL design, synthesis, static timing analysis, formal verification , PLDRC, clock domain crossing, and low power techniques. Knowledge and… more
- Google (Sunnyvale, CA)
- …static timing (ie, full chip timing signoff ownership, constraint authoring and verification , full chip static timing analysis and timing ECO creation, timing ... including clocking, timing exceptions, time budgeting, IO interface timing, ECOs, and constraint verification . In this role, you'll work to shape the future of AI/ML… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** R&D Engineer position available in design and physical implementation of high performance ... address challenges of designing in deep sub-micron processes and state-of-the-art ASIC design for AI/ computing and networking products **Qualifications :… more
- Amazon (Cupertino, CA)
- …for use by AWS internal teams. We're looking for a Senior SoC Modeling Engineer to join the team and deliver new functional models, infrastructure, and tooling for ... testing, and debug - Work closely with architecture, RTL design, design verification , emulation, and software teams to build, debug, and deploy your models… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Logic and Digital Circuit Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... of analog circuits. + You will be working with ASIC controller teams to define a unified interface +...Experience with static timing tools (nanotime, primetime) and formal verification tools + Have a strong background in Perl… more
- Lockheed Martin (Palmdale, CA)
- **Description:** The Cyber Systems Security Engineer Staff will be responsible for leading a team of fellow engineers in the designing, assembly, integration, and ... This includes network planning, hardware installation, software integration support, verification , and validation of system functionality\. In addition to designing… more
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