- Microsoft Corporation (Mountain View, CA)
- …to help achieve that mission. We are looking for a **Principal Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) ... and drive the development of microarchitecture and RTL design, coding, and verification of complex IP blocks, including: + Mixed-signal IPs + High-speed interfaces… more
- Microsoft Corporation (Mountain View, CA)
- …mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality ... and optimize the Cloud infrastructure. We are looking for a **Principal Design Engineer Manager - AI Network Silicon** to join the team. Microsoft's mission is… more
- Cisco (San Jose, CA)
- Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...coordinated in the RTL. + Work closely with the design/design- verification and PD teams to enable the integration and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …team of super star engineers to develop our next generation FPGA based verification platform. Responsibilities: + Implement new algorithm and enhancements in ... technology. We are looking for an exceptional C++ software engineer to join the Protium Software Development Team to...you are a solid contributor in the FPGA or ASIC prototyping/synthesis/ verification space and have delivered great… more
- NVIDIA (Santa Clara, CA)
- …logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification , logic synthesis, timing ... a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement...are a team that constantly evolves by adapting to new opportunities and find creative solutions to difficult problems.… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …outcomes for our customers. You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies from RTL to ... technology. This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG)...Innovus + Experience in Logic Design and Synthesis, Formal Verification , Low Power design, Physical Design and Timing Closure… more
- Google (Sunnyvale, CA)
- …Product teams to ensure that goals are met with systems and will work with ASIC /FPGA, Software, and Verification teams to ensure proper verification of ... DDR, Ethernet, USB, SPI, etc. As a Staff Hardware Engineer , you will work on Machine Learning/AI hardware systems...and product validation. + Lead the bring up, validation, New Product Introduction (NPI), deployment, and sustaining of hardware… more
- NVIDIA (Santa Clara, CA)
- …era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to take on, that only we can pursue, and that ... creativity and intelligence. Are you a Mask Layout Design Engineer ? If yes, We would love to hear from...technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration… more
- Silvus Technologies (Irvine, CA)
- …real-world communication needs. The _Senior FPGA Design Engineer_ will be based at our new Silvus office, located in **_Irvine, CA_** . The position will be on a ... test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers. + Provide support to the… more
- Meta (Sunnyvale, CA)
- …work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices ... through architecture, to firmware, and algorithms.As an SoC Physical Design Engineer at Meta Reality Labs, you will perform physical design implementation… more