• Senior Principal FPGA Design Engineer

    BAE Systems (Nashua, NH)
    …(Secret), or eligible to obtain one + Significant experience in FPGA (preferred) or ASIC Design / Development + VHDL (preferred) or Verilog HDL coding + ... Familiarity with Xilinx Vivado or Intel/Altera Quartus + Experience with internal logic analyzer (ILA/chipscope/signaltap) + Digital simulation using Modelsim/Questa + Significant experience with static timing analysis + Significant experience with clock… more
    BAE Systems (03/08/25)
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  • Principal FPGA Design Engineer

    BAE Systems (Nashua, NH)
    …(Secret), or eligible to obtain one Significant experience in FPGA (preferred) or ASIC Design / Development VHDL (preferred) or Verilog HDL coding Familiarity ... with Xilinx Vivado or Intel/Altera Quartus Digital simulation using Modelsim/Questa Significant experience with static timing analysis and clock domain crossing techniques Experience with high speed interfaces like SERDES, PCIe, DDR2/3/4, LVDS Familiarity with… more
    BAE Systems (02/21/25)
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  • Entry level FPGA Design Engineer (onsite)

    BAE Systems (Nashua, NH)
    …(Secret), or eligible to obtain one + Some experience or classwork in FPGA or ASIC Design / Development, including + VHDL (preferred) or Verilog HDL coding + ... with clock domain crossing techniques + Experience with designer-level test bench ( VHDL , Verilog, or SystemVerilog) + Familiarity with revision control (GIT, CVS,… more
    BAE Systems (05/07/25)
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  • FPGA Design Verification Engineer I

    BAE Systems (Nashua, NH)
    …random, self-checking testbenches implemented using SystemVerilog/UVM, OVM, Verilog, 'e', and/or VHDL + Experience using FPGA/ ASIC design and verification tools ... and use configurable, self-checking testbenches implemented in SystemVerilog/UVM and/or VHDL ; + Develop constrained-random, metric-driven test plans and strategies… more
    BAE Systems (04/02/25)
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  • Design Verification Engineer - FPGA - (Sign-on…

    BAE Systems (Nashua, NH)
    …and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools ... and use configurable, self-checking testbenches implemented in SystemVerilog/UVM and/or VHDL ; + Develop constrained-random, metric-driven test plans and strategies… more
    BAE Systems (03/06/25)
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  • Senior Design Verification Engineer - FPGA

    BAE Systems (Manchester, NH)
    …and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools ... and use configurable, self-checking testbenches implemented in SystemVerilog/UVM and/or VHDL ; + Develop constrained-random, metric-driven test plans and strategies… more
    BAE Systems (03/06/25)
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