• Senior DFT Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …involving crafting creative solutions for cutting edge test techniques, in-system test architecture, as well as verification and post- silicon validation on ... member in our team, you will work next generation test architectures. You will work with multi-functional teams, implementing...Tessent ATPG/SSN experience is a plus. + Experience in Silicon debug and bring-up on the ATE … more
    NVIDIA (07/01/25)
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  • Lead ASIC DFT Engineer

    Google (Mountain View, CA)
    …insertion, Automatic Test Pattern Generation (ATPG), gate level simulations and silicon debug, low power designs, Built-In Self- Test (BIST), Joint Test ... part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer...that can be used for production in the Automatic Test Equipment ( ATE ) flow. + Work with… more
    Google (08/08/25)
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  • Material & Physical Failure Analysis…

    Cisco (San Jose, CA)
    …such as LADA/TIVA/LTM/SMI/LVP/PEM/LSI + Hands on experience with ATE test , test program development or post silicon ASIC validation is a plus. + ... Material & Physical Failure Analysis Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1441249) + Location:San Jose, California, US + Alternate… more
    Cisco (08/02/25)
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  • Manufacturing Engineer , Product Operations

    Google (Sunnyvale, CA)
    …cause. + Experience with Python/SQL scripting. + Understanding of CMOS devices, fabrication processes, ATE test , DFT, quality, and reliability. Be part of a team ... at a company developing supply chains in manufacturing and test . + Experience working with ODMs, contract manufacturers, and...that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer… more
    Google (08/15/25)
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  • Senior Director, Engineering

    Skyworks (Newbury Park, CA)
    …Market:Oxnard Job Segment: RF Engineer , Electrical Engineering, Front End, Test Engineer , Database, Engineering, Technology Apply now " Find similar ... production, you will: + Architect and enforce Design For Test (DFT) and Design For Manufacturing (DFM) methodologies +...checklists at each module phase (Architecture/DEV/P0/P1) + Drive periodic ATE and FI yield and coverage reviews at each… more
    Skyworks (07/06/25)
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  • Director of Reliability

    NVIDIA (Santa Clara, CA)
    …reliability acceleration models, and failure rate estimates. + Proven understanding of ATE test methodologies, electrical parameters, and drift analysis. + ... to achieve the highest level of quality and reliability for future-generation silicon products in various markets. This role requires critical thinking, technical… more
    NVIDIA (07/25/25)
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