- NVIDIA (Santa Clara, CA)
- …role offers a great opportunity to be at the forefront of compiler verification , ensuring our brand-new technology maintains its premier standard. You will: + Design ... AI /LLM technologies. + Previous experience in compiler development, verification /testing, or performance analysis (ie, developing/testing C++ runtime libraries,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …an impact on the world of technology. Principal Software Engineer - Low-Power Verification (Palladium & Protium) We are seeking a highly skilled Senior Software ... Engineer to help build the next generation of low-power verification software for the Palladium and Protium emulation platforms. In this role, you will drive… more
- Amazon (Cupertino, CA)
- …and Japan, and customers across all industries. We are seeking experienced Design Verification Engineers to build the next generation of our cloud server chips. Our ... Degree or Higher in EE or CS or CE. - 8+ years of design verification experience using System Verilog and UVM - 8+ YOE in testbench development including: stimulus,… more
- Amazon (Cupertino, CA)
- …solutions achieve their desired functionality, developing and executing multi-faceted verification /validation plans, and measuring the teams progress towards our ... Engineering, Electrical Engineering, or other related discipline - 3+ years of design verification experience using System Verilog and UVM - 3+ years of experience… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Join us today! We are now looking for a Senior System Verification Engineer to join our Emulation division and will be working onsite from our ... of CPU - GPU coherency + Experience with UVM verification environments and scripting with Perl, Python and C/C++...5. You will also be eligible for equity and benefits (https://www.nvidia.com/en-us/ benefits /) . Applications for this job… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Verification Engineer to join our Emulation division. We are a worldwide recognized division noted for groundbreaking technology. We are ... proficient in Verilog and/or VHDL, C/C++ and SystemVerilog. + Experience with UVM verification environments and scripting with Perl, Python and C/C++ is essential. +… more
- SpaceX (Sunnyvale, CA)
- …willing to work extended hours and weekends as needed COMPENSATION AND BENEFITS : Pay range: Design Verification Engineer/Level I: $130,000.00 - $155,000.00/per ... RTL and physical design Scan Design Rule Check (DRC) tools + Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems + Running and… more
- Cedars-Sinai (Los Angeles, CA)
- …providers and Embassies to acquire authorizations for services, letters of guarantee, verification of benefits and updates of insurance coverage. + Uses ... expenses. Supports patients' billing inquires related to explanation of benefits , self-pay billing questions, patient disputes, verifications, and other billing… more
- Ford Motor Company (Sacramento, CA)
- …C/C++ or other relevant languages used in embedded software development and verification . + Experience with automated testing tools and frameworks such as Pytest, ... programs, subsidized back-up child care and more * Family building benefits including adoption and surrogacy expense reimbursement, fertility treatments, and more… more
- Butler America (Sunnyvale, CA)
- FPGA Design/ Verification Engineer Location: Sunnyvale, CA Job ID: #71390 Pay Range: $75-90 The selected candidate will be responsible for ASIC & FPGA development on ... technical direction to junior engineers. Overall contribution to design, simulation, verification , integration & test of complex, high speed products. Benefits… more