• Systems Engineer Sr Staff

    Lockheed Martin (Fort Worth, TX)
    …Matrix \(RVM\), Logic Diagrams, Interface Control Diagrams \(ICD\)s, Capability Block Flow Diagrams, Verifications and Validation Plans, and other Systems ... Matrix \(RVM\), Logic Diagrams, Interface Control Diagrams \(ICD\)s, Capability Block Flow Diagrams, Verifications and Validation Plans, and/or other Systems… more
    Lockheed Martin (08/09/25)
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  • Analog/Mixed-signal IC Design Co-Op (June '26-Dec…

    Skyworks (Austin, TX)
    …at the time of the internship, the individual will participate in block architecture definition, detailed circuit design, layout supervision, verification of the ... block , chip-level verification, and/or lab validation. Responsibilities will also include producing detailed documentation, presenting several design reviews showing… more
    Skyworks (08/08/25)
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  • Histology Technologist PRN

    HCA Healthcare (Dallas, TX)
    …histology and cytology procedures including specimen processing/fixation, cell block preparation, embedding, microtomy, slide preparation, routine stains, IHC ... case organization in accordance with department procedures. Assure positive sample, block and slide identification Prepare and maintains reagents for routine stains… more
    HCA Healthcare (08/03/25)
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  • Analog IC Design Engineer - Custom Power Products…

    Texas Instruments (Dallas, TX)
    …high performance switching regulators, translating system requirements to chip and block level architecture and specifications + Perform detailed analysis of ... fault systems and power FETs. + Experience working with layout team on block and top level floor-planning + Knowledge of device physics and process technologies… more
    Texas Instruments (07/31/25)
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  • Principal | MTS HBM DRAM Design Architect

    Micron Technology, Inc. (Richardson, TX)
    …You will need to have the ability to evaluate Full chip or block level functionality and provide solutions to help delivery of functionally accurate design. ... delivery optimization, CMOS & semiconductor device physics. + Evaluate full chip or block level functionality and provide solutions to ensure the delivery of a… more
    Micron Technology, Inc. (07/18/25)
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  • Senior Business Coordinator Internal Medicine MEO…

    UTMB Health (Galveston, TX)
    …to their accreditation requirements and participate in the implementation of master block schedules + Assists Chiefs and divisional management with distribution and ... completion and delinquent reminders to faculty and fellows + Create and track block schedules using New Innovations and cross reference with Amcon as deemed… more
    UTMB Health (07/08/25)
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  • Principal Systems Engineer (Onsite)

    RTX Corporation (Richardson, TX)
    …and sub-system test procedures. + Build advanced SysML models for activities, states, block diagrams, and use cases. + Leverage JIRA to decompose epics and features ... Architect. + Expertise in building complex SysML models, including developing activity, state, block diagrams, use cases, etc. + Agile experience as a Scrum Master,… more
    RTX Corporation (07/02/25)
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  • Sr. RTL Design Engineer - Wireless Modem, Project…

    Amazon (Austin, TX)
    …. Create standalone verification test bench to verify the correctness of your block . . Work with the verification team and participate in System level verification ... test benches constructed using UVM, System C and DPI-C. . Ensure that the block meets DFT, timing and power targets by working closely with the implementation team.… more
    Amazon (06/28/25)
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  • ASIC Verification Engineer, Blink/Ring ASIC Team

    Amazon (Austin, TX)
    …job responsibilities - Use and/or build bit accurate C models - Evaluate block and sub-systems for testability/verifiability - Write comprehensive block and ... system level testplans - Build assertions, traffic generators and scoreboards - Execute testplans and perform rigorous debug Basic Qualifications - Bachelor's degree in Electrical / Computer Engineering or related field - 6+ years experience in digital… more
    Amazon (06/04/25)
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  • Sr. Physical Design Engineer, Annapurna Labs

    Amazon (Austin, TX)
    …explore power-performance-area tradeoffs for physical design closure - Drive IO/Core block physical implementation through synthesis, floor planning, bus / pin ... Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm - Block Design using EDA tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including… more
    Amazon (06/03/25)
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