• Accounts Receivable Clerk

    Robert Half Accountemps (Los Angeles, CA)
    …meetings. * Maintain student billing accounts, including charges for after-school care, bus passes, trips, and other fees. * Support the annual enrollment contract ... Hired contract/temporary professionals are also eligible to enroll in our company 401(k) plan. Visit roberthalf.gobenefits.net for more information. (C) 2025 Robert… more
    Robert Half Accountemps (12/11/25)
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  • Senior PCIe Post-Silicon Validation Engineer

    NVIDIA (Santa Clara, CA)
    …the opportunity to have real impact in a multidimensional, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars ... or equivalent simulation tools, debug tools like Debussy, GDB). + Experience with bus protocol (eg PCI Express, SATA, USB) or interconnect verification is preferred.… more
    NVIDIA (12/11/25)
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  • Electrical Engineer

    Actalent (San Luis Obispo, CA)
    …+ Knowledge of analog and digital circuits, power supplies, and CAN bus communication. + Strong analytical and problem-solving skills. + Excellent written and ... US, Canada, Asia and Europe, Actalent serves many of the Fortune 500. The company is an equal opportunity employer and will consider all applications without regard… more
    Actalent (12/10/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and ... & lab debug. + Prior experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks, and/or caches is desirable. Ways to stand out… more
    NVIDIA (12/10/25)
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  • Senior Design for Debug Architect and Methodology…

    NVIDIA (Santa Clara, CA)
    …offers the opportunity to have real impact in a multifaceted, technology-focused company with product lines ranging from consumer graphics to self-driving cars and ... and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. + Expertise in design for… more
    NVIDIA (12/10/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars ... and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. + Great understanding of ASIC… more
    NVIDIA (12/09/25)
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  • Electrical Design Verification Tester (Edvt)

    Insight Global (San Jose, CA)
    Job Description Coming soon We are a company committed to creating inclusive environments where people can bring their full, authentic selves to work every day. We ... priorities * Good understanding of system level hardware - CPU, power, clocking, bus architectures (PCIE, USB, I2C), etc * Test product's compliance to internal… more
    Insight Global (12/09/25)
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  • FPGA Engineer - Design

    Insight Global (Saratoga, CA)
    …manual tests, unit automated tests, and system level tests. We are a company committed to creating diverse and inclusive environments where people can bring their ... Proficiency with AXI protocols (at least AXI4 family). * Knowledge of common bus interfaces (I2C, SPI, etc). * Demonstrated success working in a dynamic environment. more
    Insight Global (12/07/25)
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  • Caregiver/Personal Care Assistant - All Shifts…

    Maxim Healthcare (Redlands, CA)
    …personal care plan (if applicable) + In school setting, accompanies student on bus to and from school (if applicable) + Provides companionship by reading, listening ... Maxim Benefits: Health and Wellness Medical/Prescription, Dental, Vision, Health Advocacy ( company paid if enrolled Medical) and Health Advocate Employee Assistance… more
    Maxim Healthcare (12/06/25)
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  • Senior DFT Static Timing Analysis Engineer, Cloud

    Google (Sunnyvale, CA)
    …test methodologies. + Experience in Tessent generated DFT timing constraints, SSN bus networks and constraints and mode merging. + Experience with EDA tools ... for Applicants form (https://goo.gl/forms/aBt6Pu71i1kzpLHe2) . Google is a global company and, in order to facilitate efficient collaboration and communication… more
    Google (12/05/25)
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