- BAE Systems (San Diego, CA)
- …Other incentives may be available based on position level and/or job specifics. ** Design Verification Engineer - FPGA - (Sign-on Bonus)** **112648BR** EEO Career ... **Job Description** Picture yourself developing advanced electronic systems deployed to protect members of our armed...career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human creativity and intelligence. NVIDIA is looking for motivated System /Board Design Validation Engineers to use your creativity to work on ... the highly inventive team. What you'll be doing: + System /board level debug and validation of NVIDIA 's products...functional check, debug and build reports. + Work with design engineers, software engineers, program manager, silicon design… more
- Northrop Grumman (San Diego, CA)
- …of the following Systems Engineering activities: system requirements decomposition/derivation/flow down/traceability, architecture, high-level/detail design , ... more of the following Systems Engineering activities: system requirements decomposition/derivation/flow down/traceability, architecture, high-level/detail design ,… more
- Leidos (San Diego, CA)
- …The FPGA/Firmware design engineer will work with a multi-disciplined design team (electrical engineers, systems engineers, scientists, etc) to design ... & Security engineering development team. As a **Senior** **Firmware/FPGA Design Engineer ** in Leidos, you will be...relevant experience. + Experience with, and understanding of, FPGA system design and test. + Experience with… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part...will be responsible for the verification closure of a design module or sub- system from test-planning, UVM… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part...C ++ based verification. 10. 10+ years experience in IP/sub- system and/or SoC level verification based on SystemVerilog UVM/OVM… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part...C ++ based verification 10. 14+ years experience in IP/sub- system and/or SoC level verification based on SystemVerilog UVM/OVM… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part...will be responsible for the verification closure of a design module or sub- system from test-planning, UVM… more
- M. C. Dean (San Jose, CA)
- …(Tech Specialist 2)** is responsible for the full lifecycle of a security design from RFP development through system commissioning. This is an embedded ... requirements for system performance, installations, and sustainment programs. + Define design project scope of work based on customers' needs. + Providing high… more
- Meta (Sunnyvale, CA)
- **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... for next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a...AXI, APB, I3C, SPI, UART, etc 16. Experience using C for system verification 17. Experience in… more