• Senior Package Layout Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …package pinout incorporating system level trade-offs of pins assignment. + Help perform package routing, placement, stack-up, reference plane and power distribution ... using Cadence APD or SiP tool suite. + Propose layout design trade-offs to the...size, cost, and system performance. + Develop symbols and CAD library databases using Cadence APD design tools +… more
    NVIDIA (09/17/25)
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  • ASIC Engineer, EDA Infrastructure

    Meta (Sunnyvale, CA)
    …We are looking for individuals with experience in EDA flow and methodology, CAD /automation and ASIC infrastructure to build efficient System on Chip (SoC) and IP ... RTL2GDS flow development and support 4. Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to… more
    Meta (09/13/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and automation. + Develop ... are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs...+ MS (or equivalent experience) in Electrical or Computer Engineering with 3 years' experience in ASIC Design and… more
    NVIDIA (07/19/25)
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  • Reliability Analog Design Engineer [Remote…

    Blue Cheetah Analog Design (CA)
    …a more agile and cost effective chiplet based approach. Join our team to help usher in the chiplet era of semiconductor-based products. We provide a professional ... the gap on any reliability violations * Coordinate with CAD and PDK team members to validate that the...products General Requirements: * BS, MS, Ph.D. in electrical/ECE engineering (MSEE+ preferred) * Experienced expert in performing EM/IR… more
    Blue Cheetah Analog Design (07/09/25)
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