• Principal Solutions Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …on leading foundry flows. + Chip planning and block implementation flows. + CAD experience with setting up Analog layout tools, scripting (SKILL, TCL, UNIX), PDK ... delivery to the customer. + Collaborating with the Cadence R&D teams to help develop the layout editing and verification tools. + Understanding customer's analog… more
    Cadence Design Systems, Inc. (10/29/25)
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  • Swing Shift Machinist

    ITT (Santa Rosa, CA)
    …as an organization - to provide our customers with cutting-edge solutions to help solve their most critical needs across key global end markets. Our continuous ... commitment to evolving our capabilities as a multi-industrial technology, manufacturing and engineering leader. With a strong global footprint of more than 100… more
    ITT (10/14/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and automation. + Develop ... are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs...+ MS (or equivalent experience) in Electrical or Computer Engineering with 3 years' experience in ASIC Design and… more
    NVIDIA (11/20/25)
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  • PhD Intern, AI Research - Datasets & Benchmarks

    Autodesk (San Francisco, CA)
    …ML benchmarking, and HCI. + Design and run human experiments related to AI tool use for design. + Develop and deploy scalable data collection techniques and ... Learning, Computer Science, or a related discipline. + Excellent software engineering skills, including Machine Learning. + Experience with collecting human data… more
    Autodesk (11/13/25)
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  • Signoff Methodology Engineer - New College Grad

    NVIDIA (Santa Clara, CA)
    …flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and automation. + Develop ... We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the world's leading...See: + MS or PhD in Electrical or Computer Engineering (or equivalent experience). + Good understanding of modeling… more
    NVIDIA (11/05/25)
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  • Senior Package Layout Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …package pinout incorporating system level trade-offs of pins assignment. + Help perform package routing, placement, stack-up, reference plane and power distribution ... using Cadence APD or SiP tool suite. + Propose layout design trade-offs to the...size, cost, and system performance. + Develop symbols and CAD library databases using Cadence APD design tools +… more
    NVIDIA (10/08/25)
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  • Reliability Analog Design Engineer [Remote…

    Blue Cheetah Analog Design (CA)
    …a more agile and cost effective chiplet based approach. Join our team to help usher in the chiplet era of semiconductor-based products. We provide a professional ... the gap on any reliability violations * Coordinate with CAD and PDK team members to validate that the...products General Requirements: * BS, MS, Ph.D. in electrical/ECE engineering (MSEE+ preferred) * Experienced expert in performing EM/IR… more
    Blue Cheetah Analog Design (10/07/25)
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  • Reliability Engineer

    DoorDash (San Francisco, CA)
    …because you have + A bachelors or advanced degree in a relevant engineering discipline. + Experience facilitating DFMEAs for complex components and/or systems. + ... + Ability to write Python scripts to automate reliability tests. + Experience with CAD and shop tools to design and build fixtures and/or test rigs. + Excellent… more
    DoorDash (10/01/25)
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  • ASIC Engineer, EDA Infrastructure

    Meta (Sunnyvale, CA)
    …We are looking for individuals with experience in EDA flow and methodology, CAD /automation and ASIC infrastructure to build efficient System on Chip (SoC) and IP ... RTL2GDS flow development and support 4. Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to… more
    Meta (09/13/25)
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