- Insight Global (Milpitas, CA)
- …and jitter performance targets Own block-level schematic design and verification in Cadence or Synopsys tools, driving designs to production silicon Collaborate with ... (algorithm familiarity is helpful but secondary to circuit design) - Proficiency with Cadence or Synopsys design tools - Experience with Ethernet SerDes and retimer… more
- Insight Global (Palo Alto, CA)
- …expertise in deep sub-micron FinFET technologies, focusing on 7nm and below, employing Cadence and Mentor design and verification tools. We are a company committed ... FinFET technologies, specifically at 7nm and below. Strong knowledge of Cadence Virtuoso and Mentor Graphics Calibre. (DRC/LVS checks) Bachelor in Electrical… more
- Broadcom (San Jose, CA)
- …signal integrity and power integrity, to apply to package designs + Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK. ... + Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest **OTHER… more
- Amazon (Cupertino, CA)
- …14/16nm, 20nm, or 28nm - Block Design using EDA tools (examples: Cadence , Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification, floor ... Perl or Python Preferred Qualifications - Expertise using CAD tools (examples: Cadence , Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal… more
- Broadcom (Irvine, CA)
- …system engineering, SI/PI, and thermal teams to perform BGA substrate design using Cadence APD or equivalent tools. + Ensure package designs meet SI/PI, mechanical, ... layer count, large body, flip chip BGA packaging technology + Proficiency in Cadence Allegro APD/SIP or comparable packaging design tools. + Experience working with… more
- NVIDIA (Santa Clara, CA)
- …Methods, Algorithm and Power Distribution, Power Management Circuits/Solutions + EDA Tools ( Cadence , Synopsys) What we need to see: Must be actively enrolled in ... , VHDL, Perl, Python, SPICE, HSPICE, CMOS, FinFET , Cadence , Synopsys Click here (http://www.nvidia.com/content/dam/en-zz/Solutions/about-nvidia/careers/UR-Student-Resources.pdf) to learn more about… more
- NVIDIA (Santa Clara, CA)
- …Closure, Power and Noise Analysis, and Back-End Verification + EDA Vendor (Synopsys, Cadence , Mentor, etc.) tool suites such as: ICC2, PrimeTime , dc_shell , ... ICC2, Design Compiler, PrimeTime (Synopsys, First Encounter), Innovus, Virtuoso ( Cadence ) Click here (http://www.nvidia.com/content/dam/en-zz/Solutions/about-nvidia/careers/UR-Student-Resources.pdf) to learn more about NVIDIA,… more
- NVIDIA (Santa Clara, CA)
- …to support design work in new process technologies. + Write scripts using perl and Cadence SKILL What we need to see: + BS in Electrical Engineering or Computer ... CMOS layout, and VLSI design. + Excellent programming skills; experience with perl, Cadence SKILL. + Expertise in ICV in order to support, enhance, and debug… more
- NVIDIA (Santa Clara, CA)
- …converters, ESD structures designs in groundbreaking sub-micron CMOS technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal ... layout concepts in submicron CMOS technologies. + You are an authority with Cadence custom circuit design tools - particularly virtuoso. + Experience running and… more
- Northrop Grumman (Redondo Beach, CA)
- …Python (SW Engineering); Elasticsearch, Grafana, Tableau (Data and visualization); or Cadence Virtuoso, Keysight ADWS, ANSYS HFSS (Hardware Design); Cadence ... Assura or Siemens Calebre (Hardware verification) Primary Level Salary Range: $114,000.00 - $171,000.00 The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as… more