• Sr. Principal Analog IC Designer

    Cadence Design Systems, Inc. (San Jose, CA)
    …environment + Position requires proficiency in using CAD tools for circuit simulation, layout , and physical verification + Cadence tool experience, lab test ... At Cadence , we hire and develop leaders and innovators...impact on the world of technology. The Principal Analog IC Designer is responsible for the design and development… more
    Cadence Design Systems, Inc. (07/04/25)
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  • Sr. Manager, Analog Mixed Signal IC Design

    Teledyne (Camarillo, CA)
    …background with CMOS semiconductor IC design including performing full custom analog IC layout . + Thorough understanding of deep sub-micron layout design ... Sensors is looking for a **Sr. Manager, Mixed Signal IC Design** responsible for supporting the Read Out Integrated...Strong background with full custom circuit, block, and chip layout using Cadence Virtuoso tools, Layout more
    Teledyne (07/29/25)
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  • Foundry RF IC Technology Development…

    Broadcom (San Jose, CA)
    …circuit DC and RF electrical characterization techniques and equipment + Experience with layout and circuit simulation tools ( Cadence , Keysight ADS) + Experience ... Account, please Sign-In before you apply.** **Job Description:** Senior RF IC technology pathfinder and applications support engineer supporting multiple RF … more
    Broadcom (07/12/25)
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  • Senior Staff IC Design Engineer

    Power Integrations (San Jose, CA)
    …+ Mixed-mode integrated circuit design for switching power supply: + Simulation with Cadence tools. + Layout supervision and verification. + Preparation of test ... circuit blocks and device physics. + Understanding of digital IC design. + Familiar with Cadence simulation tools, and Verilog. + Excellent written and oral… more
    Power Integrations (08/09/25)
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  • Senior/Principal IC Design Engineer Copper…

    Insight Global (Milpitas, CA)
    …analog and mixed-signal semiconductor solutions is looking for a Senior or Principal IC Design Engineer to join their advanced connectivity team. This group develops ... a hands-on technical role requiring strong circuit-level design experience and full IC tapeout ownership. Key Responsibilities: Design and tapeout BiCMOS ICs for… more
    Insight Global (08/08/25)
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  • Senior Analog/mixed-signal IC Design…

    Cisco (San Jose, CA)
    Senior Analog/mixed-signal IC Design Engineer - Acacia Apply (https://jobs.cisco.com/jobs/Login?projectId=1443040) + Location:San Jose, California, US + Alternate ... and ultra-long haul telecommunication networks. **Meet the Team** We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog… more
    Cisco (08/08/25)
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  • Principal Product Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    At Cadence , we hire and develop leaders and innovators who want to make an impact on the world of technology. This opportunity is for an engagement focused Product ... (PE) in the Digital and Signoff Group (DSG) at Cadence . The Cadence DSG will offer you...highly competent PE team with extensive PPA tuning and Layout experience, having experience of either RTL design and/or… more
    Cadence Design Systems, Inc. (06/10/25)
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  • IC CAD Engineer

    Broadcom (San Jose, CA)
    …experience. + Expertise in the following CAD Tools: Virtuoso Studio 25.1, Cadence ADE-L/XL, Maestro, Spectre, Virtuoso Layout , Quantus QRC, Voltus-XFi/EMIR, EMX, ... This individual will be hands-on, heavily involved in day-to-day design/ layout issues and in addition, interact with EDA vendors,...release, and user support to documentation + Expert in Cadence Skill, Perl, Unix Shell and utilities + Excellent… more
    Broadcom (08/08/25)
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  • IC CAD Engineer

    Broadcom (San Jose, CA)
    …integration. + Creation of documentation and hands-on training for AMS Design & Layout engineers as needed. + Tracking and resolution of tool and technology file ... + User level familiarity with related CAD Tools: Calibre, Virtuoso Layout & Schematics, Quantus QRC/StarRC/QuickCap/Raphael, and simulation using SPECTRE/HSPICE. +… more
    Broadcom (08/08/25)
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  • R&D Engineer IC Design

    Broadcom (San Jose, CA)
    …Lines, Encoders/Decoders, PRBS GEN / Check, Clock Spines, PHYs 2. Interface with other Layout , RTL, SI etc engineers to implement & integrate the developed IP 3. ... Serializer, De-Serializer etc 3. Excellent Verilog & synthesis skills using Cadence /Synopsys tools and working programming knowledge using C/C++ and scripting… more
    Broadcom (07/03/25)
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