- Meta (Sunnyvale, CA)
- …design will enable you to contribute to all phases of the chip development. Additionally, effective collaboration and communication with Digital Design Engineers, ... Micro Architecture document (collaborator/owner), IP/SoC Design plan (collaborator) and SoC/ chip bringup/validation plan (collaborator) **Minimum Qualifications:** Minimum Qualifications: 6.… more
- Meta (Sunnyvale, CA)
- …interconnect, cache, memory hierarchy analysis 3. Own Subsystem Network on Chip (NoC) architecture specification, design and characterization 4. Lead Intellectual ... correlation analysis 14. 2+ years of experience with System on Chip (SoC) Architecture, NoCs, memory subsystems, and heterogeneous compute principles **Preferred… more
- Meta (Sunnyvale, CA)
- …Validation Engineer, Reality Labs Responsibilities: 1. Responsible for System on Chip and end-to-end system validation plan development, execution and sign-off 2. ... teams (ie, architecture, Intellectual Property, Firmware, Electrical Engineering, System on Chip , and product engineer teams) to generate validation reports for SoC… more
- Meta (Sunnyvale, CA)
- …C will enable you to contribute to all phases of the chip development. Additionally, effective collaboration and communication with Digital Design Engineers, Digital ... Micro Architecture document (collaborator/owner), IP/SoC Design plan (collaborator) and SoC/ chip bringup/validation plan (collaborator) **Minimum Qualifications:** Minimum Qualifications: 6.… more
- Amazon (Cupertino, CA)
- …US, Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... methodologies using industry-standard EDA tools (Calibre, IC Validator) - Drive chip level physical verification sign-off and closure - Perform DRC (Design… more
- Adecco US, Inc. (Moreno Valley, CA)
- …annual/bi-annual Focal Review increases are entered accurately into Kronos. Ensures the Blue Chip data is provided to agency and Corporate Payroll as required. + ... staff. + Maintain Kronos dept. listing. + Compile and submit Exempt Blue Chip and Supervisor Saturday Worked bonus files. + Provide accurate and friendly customer… more
- NVIDIA (Santa Clara, CA)
- …qualifying silicon across advanced packaging technologies (2.5D, 3D, dielets), addressing chip , package, chip -package interactions and board-level reliability. + ... Proficiency in reliability statistics, reliability acceleration models, and failure rate estimates. + Proven understanding of ATE test methodologies, electrical parameters, and drift analysis. + Ability to collaborate effectively with circuit design, process,… more
- NVIDIA (Santa Clara, CA)
- …be doing: + Invent and optimize new methods for floorplanning and chip -level optimization tools. + Develop machine learning strategies to improve efficiency of ... distributed computing, efficient memory and I/O use, etc. + Experience in chip level floorplanning, timing estimation and design optimization etc. + Familiarity with… more
- Amazon (Northridge, CA)
- …verification at various products levels including but not limited to system-on- chip (SoC) calibration algorithm verification, silicon wafer and photonics test, test ... Experience with design or test of circuit boards with complex microcontrollers, system-on- chip (SOCs), or FPGAs - Experience in design verification of high-speed… more
- Cisco (San Jose, CA)
- …with front-end RTL Design and Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and ... of simulation models, test plan, code or functional coverage, multi- chip /system simulation, and performance analysis. Minimum Qualifications: + BSEE/CS combined… more