- Cadence Design Systems, Inc. (San Jose, CA)
- …This is critical piece to meet the customer objective of timing (how fast a chip functions), area and power (the power consumption of the chip ) and congestion, ... etc. We are looking for talented candidates with expertise in C++, gdb debugging, multi-threaded frameworks and general software development skills with a strong background in electronic design automation (Logic Optimization , Power / Timing Optimization or… more
- NVIDIA (Santa Clara, CA)
- …Deliver these solutions from concept to lab. + Drive thermal solutions roadmap for chip bring-up and align across teams in the company , while managing trade-offs ... improve the design workflow and process. + Work alongside system architects, chip and board designers, and software/firmware engineers on thermal solution design and… more
- NVIDIA (Santa Clara, CA)
- …DDR, USB, UCIE) + Experience with HSIOs like PCIE or chip -to- chip interconnects including understanding of process/temp/voltage sensitivity. + Understanding ... of HSIO power management + Understanding of firmware/driver structures and their interaction with Hardware. + Strong EE fundamentals, knowledgeable in computer architecture, high speed interfaces, timing analysis, process variations, statistical error rates… more
- NVIDIA (Santa Clara, CA)
- …experience. + 8+ years experience in Physical design/Timing. + Experience in full- chip /sub- chip Static Timing Analysis (STA), timing constraints generation and ... management, and timing convergence. + In-depth understanding of multiplexed scan logic and constraints. + Expertise in physical design, optimization, and ECO implementation eg cell sizing, buffering, vt swap. + Hands-on knowledge of industry standard… more
- NVIDIA (Santa Clara, CA)
- …flows (Lint/CDC/Synthesis/DFT/LEC/STA) and coordinate with back-end teams for successful chip tape-outs + Drive silicon bring-up efforts and performance optimization ... over 8 years of overall experience in mixed signal + Proven experience in mixed-signal chip design, with 3+ years in a leadership role + Expertise in Verilog or… more
- quadric.io, Inc (Burlingame, CA)
- …from RTL to GDS across multiple advanced process nodes. + Preform test chip tape outs as necessitated by architecture innovation. + Collaborate with the architecture ... of CPU/GPU/ASIC implementation + Proficiency in TCL scripting + Proficiency in chip front-end and back-end implementation tools such as Design Compiler, PrimeTime,… more
- NVIDIA (Santa Clara, CA)
- …Mixed-Signal Design group + Interact with multi-functional groups to support chip validation and ramp to production + Characterize fundamental optical, ... electro-optical, and RF performance of new chip designs + Validate, debug, and characterize new analog, photonic, electrical-optical, and mixed-signal designs +… more
- NVIDIA (Santa Clara, CA)
- …methodology, design, testplan and tools to efficiently enable, test and deploy new chip features. The group is muti-faceted, working across SSG and other partner ... SOL, efficient testing meeting quality benchmarks. Scope spans from datacenter to chip level. + Creating productization processes and methodologies to guide SSG… more
- NVIDIA (Santa Clara, CA)
- …of GPU and SoC product platforms. The sophisticated nature of various chip features poses many exciting debugging situations. Someone with proven understanding and ... to PCB design, PCB architecture, system architecture, PCB Layout, Mechanical, Thermal, Chip Arch and product management for effective platform validation + Debug… more
- NVIDIA (Santa Clara, CA)
- …define the POR of our switch product line. + Face the most challenging Full- Chip correctness and performance issues, which cannot be handled by the units' designers ... as they require full cross-unit understanding of the chip . + Work closely with board and package design to understand the different design limitations: power, di/dt,… more