- Amazon (Cupertino, CA)
- …- MS degree in EE, CE or CS - Good breadth of knowledge in chip design from micro-architecture through physical design - Good knowledge of design verification (DV) ... simulation methodologies - Experience with large gate-level simulation setup and debug with SDF - Strong programming and scripting skills in Perl, Python or Tcl - Experience with industry standard DFT/SCAN/ATPG tools - Experience with STA constraints… more
- Sycuan (El Cajon, CA)
- …Poker game revenue by distributing cards, facilitating wagers, performing cash and chip transactions from the table bank, and maintaining impress bank according to ... established procedures. Maintains game integrity by maintaining up-to-date knowledge of game procedures and house rules, applying procedures accordingly, informing players of rules as needed, and summoning Floor Managers for all game-related decisions.… more
- Meta (Sunnyvale, CA)
- …image processing, display engineering, camera modules, mobile SoC (System on Chip ) and PMIC (Power Management Integrated Circuit) or Battery Management System ... 17. Experience leading technical teams, cross-functional groups and vendors against project plans **Preferred Qualifications:** Preferred Qualifications: 18. MS or PHD in Electrical Engineering or Computer Engineering 19. 12+ years of industry experience in… more
- Meta (Sunnyvale, CA)
- …the testing infrastructure to validate new core IP or System on Chip (SoC) implementations. You will work closely with researchers, architects and designers ... in creating test bench requirements and test cases for multiple state of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and architects defining verification plans for each of the different core… more
- Meta (Sunnyvale, CA)
- …for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will ... be part of an agile team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning,… more
- Meta (Menlo Park, CA)
- …individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be ... part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Meta's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM… more
- Meta (Sacramento, CA)
- …Verilog / UVM 8. 2. Constraint Random Testbench 9. 3. IP/SoC (System On Chip ) Verification 10. 4. Debugging design 11. 5. Functional Coverage 12. 6. Automation ... Scripting 13. 7. Regression management, AND 14. 8. Verification IP **Public Compensation:** $238,228/year to $287,650/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and… more
- Meta (Burlingame, CA)
- …control, digital control theory, optimization algorithms, feedback control algorithms, chip -level sensor design, gear-ratio optimization, dynamic system ID and ... machine learning 13. Experience with organizational and analytical skills, driving technical strategy and execution in a fast-paced, high ambiguity environment **Preferred Qualifications:** Preferred Qualifications: 14. Experience working in CM, JDM, and… more
- Meta (Sunnyvale, CA)
- …for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will ... be part of a team working with the best in the industry, focused on developing innovative ASIC solutions for Meta's data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of… more
- Meta (Sunnyvale, CA)
- …implementation from RTL to netlist for complex digital blocks or full- chip designs, responsible for floorplanning, placement, clock tree synthesis (CTS), routing, ... static timing analysis and signoff 2. Collaborate with RTL design, DFT, verification, and power teams to ensure seamless integration and secure QOR 3. Optimize for power, performance, and area (PPA) using industry-standard tools and methodologies 4. Contribute… more