- Meta (Sunnyvale, CA)
- …Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC ... Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power 2. Debug the timing/area/congestion issues and work with RTL &… more
- Meta (Sunnyvale, CA)
- …individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be ... part of a agile team working with the best in the industry, focused on developing ASIC solutions for Meta's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench… more
- Meta (Sunnyvale, CA)
- …Test (DFT) methodologies, implementation, and verification to build best-in-class System on a Chip (SOC) and IP for data center applications. We are looking for ... individuals with a background in Design for Testability (DFT) methodologies and implementation for IP/SOC, with demonstrated use and understanding of Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer, DFT… more
- Amazon (Cupertino, CA)
- …and many more. The Distributed training team works side by side with chip architects, compiler engineers and runtime engineers to create , build and tune ... distributed training solutions with Trainium. Experience training these large models using Python is a must. FSDP, Deepspeed and other distributed training libraries are central to this and extending all of this for the Neuron based system is key. Key job… more
- Broadcom (San Jose, CA)
- …Debug, Silicon Characterization etc. is a plus + Experience or familiarity in back-end chip design, Timing, CDC flows is a plus + Strong Pre/Post Silicon debugging, ... analytical and independent problem solving ability. + Must be a team player with good verbal and written communication skills. + Must be self-driven engineer with good project management and organizational skills to deliver high quality output in a timely… more
- Skyworks (Irvine, CA)
- …to the following: * Working with experienced engineers to validate/develop multi- chip modules * Measuring RF module performance across supply, temperature, and ... frequency * Creating compliance matrices against spec, plotting results and analyzing data * Participating and presenting in data reviews * Performing lab testing using standard RF test equipment * Troubleshooting and resolving test/bench or technical issues *… more
- Meta (Sunnyvale, CA)
- …match the real and virtual worlds throughout the day.As an Analog Mixed Signal Chip Application Engineer at Meta, you will work with a group of engineers creating ... high-performance and low-power custom designs for our Augmented Reality/Virtual Reality chips. Special focus areas will include breakthrough displays, sensors, interconnects and power. Your primary responsibility will include interfacing with analog mixed… more
- Meta (Sunnyvale, CA)
- …applications **Preferred Qualifications:** Preferred Qualifications: 10. Experience in leading chip development from Architecture to Tapeout 11. Experience in ... data-path development 12. Experience in CPU, Network protocols, NOC, Memory and Peripheral Subsystems 13. Experience with Synthesis, Timing Closure and Formal Verification Methodology 14. Master's or PhD degree in Electrical Engineering, Computer Science or… more
- NVIDIA (Santa Clara, CA)
- …experience. + Proven experience working in an architecture validation or full chip verification environment. + Strong problem-solving and debugging skills, with a ... track record of driving issues to closure. + Proficient programming skills in C++, C, and scripting languages such as Python. + Experience using Z3 SMT solver preferred but not required + Solid background in Computer Architecture with experience in binning and… more
- Cisco (San Jose, CA)
- …Experience working with cooling or Liquid cooling technologies such as Direct to chip , Immersion cooling. + Experience working with cluster scale testing. Ideally on ... AI infrastructure or optimizing UCS compute & AI infrastructure to support high-performance AI/ML training and inference. **Preferred Qualifications** + Understanding of high-performance computing AI workloads, and other AI infrastructure components. +… more