- Amazon (Sunnyvale, CA)
- …of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. ... you will: . Implement wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level… more
- Broadcom (San Jose, CA)
- …use of various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design + Working knowledge of IP and chip design flow for analog ... for validation before product manufacturing + Provide design rule reviews for IP, chip , and package designs for product release sign off + Provide support for… more
- Amazon (San Diego, CA)
- …of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. ... you will: . Implement wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level… more
- NVIDIA (Santa Clara, CA)
- …GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Help in driving frontend and backend implementation including synthesis, ... 2+ years experience in Synthesis and Timing + Hands-on experience in full- chip /sub- chip Static Timing Analysis (STA), timing constraints generation and… more
- Amazon (San Diego, CA)
- …with RTL/RFIC designers, communication systems and software engineers to drive chip and system specifications . Develop and optimize HW/SW calibration algorithms ... characterization of RF Wireless SOC performance . Involve in chip bring-up in the lab and optimize conducted and/or...Experience in using lab equipment, bring-up and validation of chip . MSEE/PhD is highly preferred with emphasis on… more
- Amazon (Sunnyvale, CA)
- …methodology and implementing the corresponding test plan for sub-systems and the full chip . You will participate in the design verification and bring-up of the ... chip and subsystems by writing relevant assertions, debugging code,...Deliver detailed test plans for verification of the full chip or sub-system by working with design engineers and… more
- NVIDIA (Santa Clara, CA)
- …systems are architected and built, has intimate knowledge of digital design, and understands chip development cycles, this is your place to be. What You'll Be Doing: ... + Drive day to day execution of chip architecture for NVIDIA's innovative NVLink Fusion platform +...verification, PD, and IP teams. Join the future of chip design, you will work on groundbreaking products with… more
- SpaceX (Sunnyvale, CA)
- …at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. RESPONSIBILITIES: + Work with the ... integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with… more
- NVIDIA (Santa Clara, CA)
- …closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Work with PD, DFX, Clocks, and other teams in coming up with ... years experience in Timing and STA + Hands-on experience in full- chip /sub- chip Static Timing Analysis (STA) and timing convergence, timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- …in a few of the following areas: + HSIOs like PCIE or chip -to- chip interconnects including understanding of process/temp/voltage sensitivity on BER. + ... Identifying full chip data paths for HSIO saturation and working with applications to stress test for stability, perf, and power. + System level and interconnect… more