• Signal and Power Integrity Engineer, Machine…

    Google (Sunnyvale, CA)
    …from concept to production. You will collaborate within a cross-functional team, including Chip Design , Intellectual Property (IP), System Design , Software, ... for High-Performance Computing (HPC) based on 2.5D/3D package technology. + Collaborate with chip design team, system design teams and suppliers to drive … more
    Google (08/28/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …years' experience in Physical Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and ... inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer(s) - PPA Fusion Compiler to join our outstanding… more
    NVIDIA (06/10/25)
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  • Senior Physical Design Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …years experience in Physical Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and ... and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer(s) to join our outstanding Networking Silicon engineering… more
    NVIDIA (06/10/25)
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  • Design Engineer

    Applied Materials (Santa Clara, CA)
    …more about our benefits (https://hrportal.ehr.com/applied/) . **Key Responsibilities** + Overall chip design knowledge with hands on experience/projects in at ... materials engineering solutions used to produce virtually every new chip and advanced display in the world. We ...chip and advanced display in the world. We design , build and service cutting-edge equipment that helps our… more
    Applied Materials (08/07/25)
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  • Physical Design Flow and Methodology…

    Google (Sunnyvale, CA)
    …Physical Design EDA CAD tool workflows for ASIC development. + Collaborate with chip design teams to implement tools and methodologies for physical design ... in a semiconductor environment. + Experience developing automated physical design workflows from RTL to GDS, utilizing Tcl, Python,...this role, you will be a part of the chip implementation team developing flows and methodologies for workflow… more
    Google (08/28/25)
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  • Manager, Digital Design - Mixed-Signal…

    NVIDIA (Santa Clara, CA)
    …and over 8 years of overall experience in mixed signal + Proven experience in mixed-signal chip design , with 3+ years in a leadership role + Expertise in Verilog ... Are you looking for a Digital Design Manager role? As a Senior Digital ...flows (Lint/CDC/Synthesis/DFT/LEC/STA) and coordinate with back-end teams for successful chip tape-outs + Drive silicon bring-up efforts and performance… more
    NVIDIA (06/10/25)
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  • Sr. RF Module Design Engineer

    Skyworks (San Jose, CA)
    …plater with effective communication skills. Experience with RF power amplifier, multi- chip module/high-speed PCB, RF front-end design , and product development ... a uniquely large impact on the success of the company. Responsibilities + Design multi- chip module/PCB and RF front-end modules targeting cellular applications +… more
    Skyworks (07/06/25)
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  • Design Automation Engineer

    Broadcom (San Jose, CA)
    …various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design + The ideal candidate will have wide-ranging experience, with a ... already have a Candidate Account, please Sign-In before you apply.** **Job Description:** ** Design Automation Engineer** This position is part of a team tasked with… more
    Broadcom (07/28/25)
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  • Research Scientist, Circuit Design (PhD)

    Meta (Sunnyvale, CA)
    …existing HW 14. Experience using generative AI models and solutions 15. Experience with chip design flow and chips tape-out 16. Must obtain work authorization in ... state-of-the-art accelerators and SoCs. **Required Skills:** Research Scientist, Circuit Design (PhD) Responsibilities: 1. Identify and solve multi-discipline AI and… more
    Meta (08/26/25)
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  • DFT Design Engineer, AWS Machine Learning…

    Amazon (Cupertino, CA)
    …Qualifications - MS degree in EE, CE or CS - Good breadth of knowledge in chip design from micro-architecture through physical design - Good knowledge of ... member of the Silicon Optimization Engineering Team you'll be responsible for the design and optimization of hardware in our data centers. You'll provide leadership… more
    Amazon (08/04/25)
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