- NVIDIA (Santa Clara, CA)
- …distributed computing, efficient memory and I/O use, etc. + Experience in chip level floorplanning, timing estimation and design optimization etc. + ... with particular interest in EDA strategies and algorithms for floorplanning, design estimation, and optimization. Such optimization usually includes a mix of… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Senior SoC Design -STA Engineer to continue to innovate on behalf of our customers. We are a part ... and Crosstalk Noise analysis for digital ASIC/SoCs. * Full chip timing constraints development, full chip /...& Route and other local/remote teams to address the design challenges in the context of timing sign-off. *… more
- NVIDIA (Santa Clara, CA)
- …crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip . The clocks ... team to help craft the physical floorplan of the chip . The team explains the programming model to the...the clock domain to satisfy functional, physical and testing design requirements. + Engage with multiple teams and … more
- NVIDIA (Santa Clara, CA)
- …working with offshore teams preferred. + A background in board PDN design and in-depth knowledge of chip -and board-level dI/dt analysis/mitigation techniques ... and silicon features, correlate silicon behavior with simulations, and provide design feedback. + Driving new feature initiatives across multiple business units,… more
- Microsoft Corporation (Mountain View, CA)
- …and optimize the Cloud infrastructure. We are looking for a **Senior Design Verification Engineer** to join the team. **Responsibilities** + Establish yourself as ... an integral member of a design verification team for the development of AI components...delivering complex Application Specific Integrated Circuits(ASIC) or System on Chip (SOC). **Other requirements:** Ability to meet Microsoft, customer and/or… more
- Amazon (San Diego, CA)
- …communities around the world. Come work at Amazon! We're hiring a Sr. RTL Design Engineer - Wireless Modem within a high performance ASIC design team. ... Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites...and system engineers to drive hardware micro-architecture. - Lead design of 1 or more DSP data path modules… more
- Amazon (San Diego, CA)
- …of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. ... you will: . Implement wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level… more
- NVIDIA (Santa Clara, CA)
- …GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Help in driving frontend and backend implementation including synthesis, ... 2+ years experience in Synthesis and Timing + Hands-on experience in full- chip /sub- chip Static Timing Analysis (STA), timing constraints generation and… more
- Amazon (Cupertino, CA)
- …resources here to help you develop into a better-rounded professional. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers...Curious" mindset About the team Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning… more
- SanDisk (Milpitas, CA)
- … level integration, chip lead, and full product life cycle (requirements, design , implementation, test) of Logic design + Working knowledge of the entire ... Engineer to lead and deliver projects for our Memory Design team. This is a great opportunity for a...revenue opportunities for the company. Join the Memory Technology Design Team and become a leader of this highly… more