• Package Design Engineer

    Meta (Menlo Park, CA)
    …create as part of a world-class engineering team. **Required Skills:** Package Design Engineer Responsibilities: 1. Drive chip -package-system co- design by ... thermal and electrical analysis 4. Involvement and how they use package design to improve the chip , what kind of hands on experience (Derek for preS). They will… more
    Meta (08/01/25)
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  • Staff R&D Engineer Adv Tech Dev

    Broadcom (San Jose, CA)
    …and use of various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design + Working knowledge of IP and chip design flow ... technology & packaging for validation before product manufacturing + Provide design rule reviews for IP, chip , and package designs for product release sign off +… more
    Broadcom (07/11/25)
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  • Principal Physical Design Engineer, ATG

    NVIDIA (Santa Clara, CA)
    …15+ years of relevant industry experience + Experience in large VLSI physical design chip implementation on advanced silicon node technologies + Track record ... Group is looking for a highly motivated Principal Physical Design Engineer to join our group. Do you have...analysis, process nodes and experience of flow development and chip implementation all the way to GDS tapeout? Have… more
    NVIDIA (07/31/25)
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  • RF Module Engineer - Summer/Fall Co-Op

    Skyworks (San Jose, CA)
    …for the fast-paced and highly competitive cellular handset market. + As a Multi- Chip Module Design Engineer, you will be responsible for developing ... and systems engineering team to translate customer specifications into design requirements at the multi- chip module (MCM) level. + You will be responsible for… more
    Skyworks (08/16/25)
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  • Virtual Platform Hardware Modeling Engineer

    Meta (Sunnyvale, CA)
    …hardware accelerators 9. High proficiency in modern C++ in the domains of chip - design , electronic design automation or simulation 10. General familiarity ... processes. **Required Skills:** Virtual Platform Hardware Modeling Engineer Responsibilities: 1. Design and develop SystemC TLM models to accurately represent the… more
    Meta (08/13/25)
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  • Design Verification Engineer (Silicon…

    SpaceX (Irvine, CA)
    …results + Experience with scripting languages, eg Python for automation + RTL design , chip bring-up, and post-silicon validation experience + Ability to work ... Design Verification Engineer (Silicon Engineering) Irvine, CA Apply...Python and MATLAB programs + Contribute towards pre-silicon verification, chip bring-up and post-silicon validation + Be a hands-on… more
    SpaceX (06/21/25)
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  • Application engineer II

    Applied Materials (Santa Clara, CA)
    …science & engineering, chemical engineering, electrical engineering (specialization in VLSI/ chip design ), metallurgy or mechanical engineering with ... science & engineering, chemical engineering, electrical engineering (specialization in VLSI/ chip design ), metallurgy or mechanical engineering with… more
    Applied Materials (08/15/25)
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  • Senior AI Infrastructure Software Engineer

    NVIDIA (Santa Clara, CA)
    …fueled by great technology-and amazing people. As part of Nvidia's applied AI team for chip design , you will have the opportunity to tap into the unlimited ... AI Infrastructure team and help build the future of accelerated computing and chip design . #LI-Hybrid Your base salary will be determined based on your location,… more
    NVIDIA (07/17/25)
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  • Lead Architect - NVLink Fusion

    NVIDIA (Santa Clara, CA)
    …solutions across design , verification, PD, and IP teams. Join the future of chip design , you will work on groundbreaking products with a dedicated team! Your ... SoC systems are architected and built, has intimate knowledge of digital design , and understands chip development cycles, this is your place to be. What You'll… more
    NVIDIA (06/19/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    …IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. + ... -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the … more
    Cisco (07/22/25)
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