- Applied Materials (Santa Clara, CA)
- …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our… more
- Applied Materials (Santa Clara, CA)
- …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our… more
- Applied Materials (Santa Clara, CA)
- …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our… more
- Applied Materials (Santa Clara, CA)
- …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our… more
- Applied Materials (Santa Clara, CA)
- …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our… more
- Amazon (Cupertino, CA)
- …- MS degree in EE, CE or CS - Good breadth of knowledge in chip design from micro-architecture through physical design - Good knowledge of design verification (DV) ... simulation methodologies - Experience with large gate-level simulation setup and debug with SDF - Strong programming and scripting skills in Perl, Python or Tcl - Experience with industry standard DFT/SCAN/ATPG tools - Experience with STA constraints… more
- SanDisk (Milpitas, CA)
- …and high-speed data path circuit design. + Perform block level and full chip circuit simulations to meet all performance specifications. + Conduct silicon debugging ... and evaluation with micro-probing. + Collaborate with characterization engineers to fully characterize silicon, and partner with other designers to develop solutions for silicon issues. + Generate detailed technical reports and presentations;… more
- Broadcom (San Jose, CA)
- …synthesis, static timing analysis. You will either be responsible for block and/or chip level design and integration. Job Requirements BSEE/MSEE. Minimum 8 years of ... experience developing, implementing, and testing high performance communications/networking ASIC products. Experience in mapping communications algorithms or standards (802.3 Ethernet) to hardware and understanding of system design tradeoffs for high volume… more
- NVIDIA (Santa Clara, CA)
- …doing: + Responsible to Floor Planning and Place and route (P&R) of High-performance chip partitions. + Integration on Analog IO's and macros. + Work on power grid ... planning, Clock tree Synthesis (CTS) and timing closure. + Multi mode and multi corner timing closure, RC extraction, Cross talk, IR drop and EM analysis. + Work with the Front-end teams to update and tune timing constraints. + Debugging timing violations and… more
- Broadcom (Irvine, CA)
- …PnR, timing closure, physical verification. + Perform blocks IR/EM analysis. Experience with chip level IR/EM analysis is a big plus. + Familiar with scripting ... languages such as tcl, perl and python. Write scripts to automate physical design flow and make it more efficient. + Expertise on low power IC design is desirable. + Good knowledge on physical verification using Mentor's Calibre tool. Minimum requirements:… more