• Senior HSIO Validation Engineer

    NVIDIA (Santa Clara, CA)
    …Simulation, diagnostics, ATE, firmware, driver, and marketing teams to drive the chip into production. + Develop new methodologies to improve the silicon validation ... process, which will help meet upcoming performance, adaptability, and safety industry standards. + Ensure interoperability with connected devices and system components in sophisticated interconnect topologies. + Engage proactively with multi-functional… more
    NVIDIA (05/29/25)
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  • Senior VLSI Design Engineering (New College Grad,…

    SanDisk (Milpitas, CA)
    …following roles at Sandisk: **Essential duties and responsibilities:** + **AI-Enhanced Chip Design** - Design Engineers will be responsible for designing, ... developing, modifying and evaluating Chip architecture circuit structures for feasibility study of high-performance...including new, most advanced 3-dimentional NAND memories. A design engineer will focus on developing technologies related to AI.… more
    SanDisk (07/19/25)
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  • Silicon Architect, Reality Labs

    Meta (Sunnyvale, CA)
    …SoCs or complex IP-based subsystems as a Silicon Architect or Digital Design Engineer 7. Experience in evaluating trade-offs such as speed, performance, power, area ... **Preferred Qualifications:** Preferred Qualifications: 10. Experience architecting or designing chip pervasive logic such as clock generation, reset, and power… more
    Meta (08/01/25)
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  • Principal Platform Architect, Agentic AI

    NVIDIA (Santa Clara, CA)
    …by great technology-and amazing people. As part of Nvidia's applied AI team for chip design, you will have the opportunity to tap into the unlimited potential of ... AI and change the landscape of the chip industry. Our team operates at the intersection of...working for us. Are you a creative and autonomous engineer who loves a challenge? Come join our applied… more
    NVIDIA (07/01/25)
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  • RF Design Engineering Co-Op (Jan '26 - June '26)

    Skyworks (Irvine, CA)
    …knowledge and skills while contributing to the design and optimization of multi- chip modules for the cellular handset market. Responsibilities + Working with ... experienced engineers to design/develop multi- chip modules + Evaluating and optimizing prototypes of multi- chip modules + Running simulations using design tools… more
    Skyworks (08/09/25)
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  • Sr. RFIC Layout Designer (Silicon Engineering)

    SpaceX (Sunnyvale, CA)
    …at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. RESPONSIBILITIES: + Work with the ... integrated circuit designers and chip leads to determine the chip floor...and ground distribution as well as working with packaging engineer to determine pad locations + Accurately estimate the… more
    SpaceX (08/25/25)
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  • AR Silicon Graphics and Modeling Architect

    Meta (San Diego, CA)
    **Summary:** We are currently seeking a Graphics Modeling Engineer to support the development of a custom graphics pipeline optimized for Mixed Reality systems. As ... features and use cases 3. Support all phases of Silicon System on Chip (SoC) development from a graphics pipeline modeling perspective - from early definition… more
    Meta (08/14/25)
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  • Advanced Packaging Modeling Expert

    Applied Materials (Santa Clara, CA)
    …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... are looking for an expert, highly experienced Senior FEA Engineer to join our Advanced Packaging Modeling team. This...risks across a wide range of package architectures (eg, flip- chip , fan-out, 2.5D/3D IC, chiplet-based designs, TSVs). + Conduct… more
    Applied Materials (08/14/25)
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  • SOC Design - STA, Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …powering the latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers. We are a part of ... and Crosstalk Noise analysis for digital ASIC/SoCs. * Full chip timing constraints development, full chip /...* Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex,… more
    Amazon (08/01/25)
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  • Service Product Line Management - (E3, Sr)

    Applied Materials (Santa Clara, CA)
    …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... job description:** Service PLM (Product Line Management) is a Technology oriented engineer , focusing on BU (Business Unit) products (eg, DRSEM, CDSEM, OPWI) and… more
    Applied Materials (08/21/25)
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