• Sr. Emulation Engineer

    Amazon (Sunnyvale, CA)
    …. Support the PostSi team to test the validation scripts on emulator. . Run chip level use case scenarios of complex blocks to ensure functional correctness . Work ... of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways.… more
    Amazon (08/22/25)
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  • Security Engineer - Semiconductor, Devices…

    Amazon (Sunnyvale, CA)
    …used in Project Kuiper. This team partners with business team and performs chip level security testing, secure chip architecture design and advisory, system ... review, security review for Secure boot code, bootloader code and firmware. In this role, you will: *Help guide the secure development of devices at Amazon, from security design, threat modeling to code reviews, security testing and fuzzing *Propose, research… more
    Amazon (08/15/25)
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  • Senior Optical Test and Automation Engineer

    Google (Sunnyvale, CA)
    …with an advanced degree. + 4 years of experience working on wafer-level or chip -level probe testing or optical lab automation and scripting (eg, Python, MATLAB, or ... + Operate electrical and optical probe stations at the wafer, die, chip , and module levels, conduct high-frequency measurements, and analyze wafer data for… more
    Google (08/13/25)
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  • Silicon Engineer , Digital Design, Quantum…

    Google (Mountain View, CA)
    …Knowledge in at least one of these areas: CPU Processor Cores, Buses/Fabric/Network-on-a- Chip , Debug/Trace, Interrupts, or Clocks/Reset. Be part of a team that ... colleagues to design or use these blocks. + Implement block-level and chip -level RTL with production-level quality (eg, Lint/CDC/FV/UPF checks). + Participate in… more
    Google (08/08/25)
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  • Senior Packaging Process Engineer

    Applied Materials (Santa Clara, CA)
    …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... role's focus is 3D packaging and hybrid bonding. Must have skills are: flip chip assembly, 2.5D / 3D packaging, wafer level assembly, and hybrid bonding. **Business… more
    Applied Materials (08/07/25)
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  • Design Engineer , Senior Director

    Applied Materials (Santa Clara, CA)
    …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... package designs. + Collaboration: Work closely with cross-functional teams, including chip designers, system engineers, and manufacturing teams, to ensure package… more
    Applied Materials (08/07/25)
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  • Principal Software Engineer (Synthesis…

    Cadence Design Systems, Inc. (San Jose, CA)
    …This is critical piece to meet the customer objective of timing (how fast a chip functions), area and power (the power consumption of the chip ) and congestion, ... etc. We are looking for talented candidates with expertise in C++, gdb debugging, multi-threaded frameworks and general software development skills with a strong background in electronic design automation (Logic Optimization , Power / Timing Optimization or… more
    Cadence Design Systems, Inc. (06/14/25)
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  • Senior Thermal Solutions Design Engineer

    NVIDIA (Santa Clara, CA)
    …Deliver these solutions from concept to lab. + Drive thermal solutions roadmap for chip bring-up and align across teams in the company , while managing trade-offs ... improve the design workflow and process. + Work alongside system architects, chip and board designers, and software/firmware engineers on thermal solution design and… more
    NVIDIA (06/13/25)
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  • Physical Design Methodology Engineer

    quadric.io, Inc (Burlingame, CA)
    …from RTL to GDS across multiple advanced process nodes. + Preform test chip tape outs as necessitated by architecture innovation. + Collaborate with the architecture ... of CPU/GPU/ASIC implementation + Proficiency in TCL scripting + Proficiency in chip front-end and back-end implementation tools such as Design Compiler, PrimeTime,… more
    quadric.io, Inc (06/09/25)
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  • Lead Speed and Reliability Engineer - DFP

    NVIDIA (Santa Clara, CA)
    …methodology, design, testplan and tools to efficiently enable, test and deploy new chip features. The group is muti-faceted, working across SSG and other partner ... SOL, efficient testing meeting quality benchmarks. Scope spans from datacenter to chip level. + Creating productization processes and methodologies to guide SSG… more
    NVIDIA (05/29/25)
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