• IC Package Design Engineer

    Actalent (San Jose, CA)
    IC Package Design Engineer - Flip- Chip BGA / High-Speed ASICs Our client, a global leader in advanced semiconductor technologies, is seeking an experienced IC ... Package Design Engineer to support the development of complex flip- chip BGA packages for cutting-edge ASICs. This role is...specialized experts who drive scale, innovation and speed to market . With a network of almost 30,000 consultants and… more
    Actalent (08/21/25)
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  • ASIC Package Engineer

    Meta (Sunnyvale, CA)
    …team. **Required Skills:** ASIC Package Engineer Responsibilities: 1. Drive chip -package-system co-design optimization for High Performance Computing using 2.5D/3D ... and feasibility studies for AI/ML and networking applications including single- chip , multi- chip , and SiP/module packaging 5. Collaborate cross-functionally… more
    Meta (08/13/25)
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  • Silicon Architect, Reality Labs

    Meta (Sunnyvale, CA)
    …firmware developers, and program managers to accelerate the development and market introduction of low power highly customized SoCs. **Required Skills:** Silicon ... **Preferred Qualifications:** Preferred Qualifications: 10. Experience architecting or designing chip pervasive logic such as clock generation, reset, and power… more
    Meta (08/01/25)
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  • Senior Synthesis Flow CAD Engineer

    NVIDIA (Santa Clara, CA)
    …of the GPU in 1999 sparked the growth of the PC gaming market , redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep ... and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology! We're responsible for the Front-End Design Implementation methodology… more
    NVIDIA (06/10/25)
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  • Director, Hardware Product Management

    NVIDIA (Santa Clara, CA)
    We're seeking a seasoned product leader to drive the strategy and go-to- market execution for our Edge AI platforms, which comprise the NVIDIA Jetson, IGX, and ... Be Doing: + Product Leadership: Lead the development and go-to- market strategy for our edge AI platforms + Team...and sensor partners to drive platform adoption. + From Chip to System: You'll have experience in the entire… more
    NVIDIA (08/29/25)
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  • SOC Design - STA, Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. * Full chip timing constraints development, full chip / Sub-System STA and Signoff ... shell and drive to automate flows. * Proficiency in chip front-end and back-end implementation tools such as Fusion...this position ranges from $129,800/year in our lowest geographic market up to $212,800/year in our highest geographic … more
    Amazon (08/01/25)
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  • Sr. ASIC Modem Design Engineer, Project Kuiper

    Amazon (Sunnyvale, CA)
    …of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. ... wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power...this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic … more
    Amazon (07/12/25)
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  • Senior ASIC Design Engineer, Project Kuiper

    Amazon (San Diego, CA)
    …of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. ... wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power...this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic … more
    Amazon (07/09/25)
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  • Sr. DSP and Wireless Systems Engineer, Digital RF…

    Amazon (San Diego, CA)
    …with RTL/RFIC designers, communication systems and software engineers to drive chip and system specifications . Develop and optimize HW/SW calibration algorithms ... characterization of RF Wireless SOC performance . Involve in chip bring-up in the lab and optimize conducted and/or...this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic … more
    Amazon (06/28/25)
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  • Senior ASIC Physical Design and Timing Engineer

    NVIDIA (Santa Clara, CA)
    …of the GPU in 1999 sparked the growth of the PC gaming market , redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep ... in 1999 sparked the growth of the PC gaming market , redefined modern computer graphics, and revolutionized parallel computing!...and SoCs at block level, cluster level, and/or full chip level. + Help in driving frontend and backend… more
    NVIDIA (08/23/25)
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