• Chip Lead, Silicon

    Google (Mountain View, CA)
    …working in a silicon organization. + 5 years of experience working as a Chip Lead. ** Preferred qualifications:** + Master's degree or PhD in Electrical ... in supporting the Post Silicon testing and taking the chip to production. Be part of a team that...share more about the specific salary range for your preferred location during the hiring process. Please note that… more
    Google (08/08/25)
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  • Chip Packaging Engineering Manager

    Google (Sunnyvale, CA)
    …production. + 3 years of industry experience in engineering management. ** Preferred qualifications:** + Master's degree or PhD in Electrical Engineering, Computer ... share more about the specific salary range for your preferred location during the hiring process. Please note that.... **Responsibilities:** + Lead and manage a team developing chip packages for Google TPUs. + Provide technical mentorship… more
    Google (08/08/25)
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  • Technical Program Manager III, Embedded, Pixel

    Google (Mountain View, CA)
    …mobile software development. + Experience with hardware/software programs, or System on a Chip (SoC)/embedded chip bring up. ** Preferred qualifications:** + ... Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed… more
    Google (08/08/25)
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  • Senior Package Layout Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …is a plus + Proven experience in substrate layout of wire bond and flip chip packages, preferred + Significant background with Cadence APD or SiP and/or PCB ... layout tools (including Constraint Manager) + Solid understanding of high-speed design signal integrity practices + Experience with Virtuoso and Calibre is a plus + Experience using Valor is helpful NVIDIA is widely considered to be one of the technology… more
    NVIDIA (07/10/25)
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  • Sr. DSP and Wireless Systems Engineer, Digital RF…

    Amazon (San Diego, CA)
    …various DSP algorithms . Experience in using lab equipment, bring-up and validation of chip . MSEE/PhD is highly preferred with emphasis on digital signal ... with RTL/RFIC designers, communication systems and software engineers to drive chip and system specifications . Develop and optimize HW/SW calibration algorithms… more
    Amazon (06/28/25)
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  • Signal and Power Integrity Engineer, Machine…

    Google (Sunnyvale, CA)
    …Integrity (SI/PI) fundamental concepts, microwave theory, or analog circuit design. ** Preferred qualifications:** + Experience in AMS (Analog Mixed Signal) design. + ... Integrity (SI/PI) analysis and design for high-speed digital systems, including chip -package co-design concepts. + Experience with SIPI or microwave modeling tool… more
    Google (08/08/25)
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  • Senior Circuit Characterization Engineer

    NVIDIA (Santa Clara, CA)
    …problem solving, collaborative, and interpersonal skills. Experience working with offshore teams preferred . + Knowledge of chip and board level dI/dt ... analysis/mitigation techniques and board PDN design background is highly desirable. + Hands-on experience with silicon bringup, frequency and power characterization, Tester to System correlation, lab equipment (oscilloscopes, multimeters, DAQ, Spectrum… more
    NVIDIA (05/29/25)
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  • Package Design Engineer

    Meta (Sunnyvale, CA)
    …team. **Required Skills:** Package Design Engineer Responsibilities: 1. Drive chip -package-system co-design by driving signal and power integrity requirements ... analysis and optimization to involved in the product definition and optimize chip floorplan, power tree structure, netlists, etc for High Performance Computing based… more
    Meta (08/01/25)
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  • Sr. Technical Program Manager - Fab, AWS Center…

    Amazon (Pasadena, CA)
    …team is innovating to produce a core element of a quantum computer - the chip . We are looking for a senior technical program manager to support our internal ... chip fabrication efforts. You will work with the management...Even if you do not meet all of the preferred qualifications and skills listed in the job description,… more
    Amazon (07/08/25)
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  • ASIC Implementation Engineer - Timing

    Meta (Sunnyvale, CA)
    …Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC ... up with IO budgets for the various partition blocks 2. Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes 3. Perform STA for… more
    Meta (08/01/25)
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