• ASIC Power Implementation Engineer, Silicon

    Google (Mountain View, CA)
    …digital ASIC design including UPF/CPF, multi-voltage domains, power gating and on chip power management. + Experience in design and analysis of power management ... innovative schemes to achieve power reduction from circuit to system level. + Develop methodology and tools for implementing...for blocks and top-level using EDA tools and roll-up full- chip power. Google is proud to be an equal… more
    Google (08/08/25)
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  • Technical Program Manager III, Embedded, Pixel

    Google (Mountain View, CA)
    …+ Experience with mobile software development. + Experience with hardware/software programs, or System on a Chip (SoC)/embedded chip bring up. **Preferred ... qualifications:** + 5 years of experience managing cross-functional or cross-team projects. + Experience shipping software for complex silicon and hardware products. + Experience with release management, with Android OS. + Experience releasing technical… more
    Google (08/08/25)
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  • ASIC Engineer, Physical Design

    Meta (Sunnyvale, CA)
    …from RTL to GDSII in low power and high-performance designs to build efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ... or Shell **Preferred Qualifications:** Preferred Qualifications: 17. Experience in full chip floor planning, partitioning, budgeting, and power grid planning 18.… more
    Meta (08/07/25)
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  • Design Engineer, Senior Director

    Applied Materials (Santa Clara, CA)
    …of package designs. + Collaboration: Work closely with cross-functional teams, including chip designers, system engineers, and manufacturing teams, to ensure ... global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service… more
    Applied Materials (08/07/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    …will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. **Key ... Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in- system test, debug and diagnostics needs of the designs. + Responsible… more
    Cisco (07/22/25)
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  • Focal Plane Engineer

    Teledyne (Camarillo, CA)
    …+ Work closely with Control Account Managers (CAMs), Program Managers and System Engineers to provide overall technical leadership for effective project planning, ... with diverse teams in crystal material growth, array detector fabrication, flip- chip hybridization, sensor assembly and performance testing to leverage existing or… more
    Teledyne (07/04/25)
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  • Manager, Digital Design - Mixed-Signal High-Speed…

    NVIDIA (Santa Clara, CA)
    …key IPs in sophisticated SoCs. You'll collaborate closely with analog designers, system architects, and other engineering teams to drive innovation and deliver ... flows (Lint/CDC/Synthesis/DFT/LEC/STA) and coordinate with back-end teams for successful chip tape-outs + Drive silicon bring-up efforts and performance optimization… more
    NVIDIA (06/10/25)
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  • Service Product Line Management - (E3, Sr)

    Applied Materials (Santa Clara, CA)
    …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... leading companies on the semiconductor industry to enable high volume chip manufacturing and wafer fabrication. Our services include the installation, maintenance… more
    Applied Materials (08/21/25)
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  • Process Engineer - (E3)

    Applied Materials (Santa Clara, CA)
    …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service… more
    Applied Materials (08/20/25)
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  • Scientist, Functional Sciences

    Bristol Myers Squibb (Redwood City, CA)
    …co-cultures, organoids, human derived iPSC, primary cells, micropatterned 2D culture, tissue-on-a- chip , or other 3D models. + Design scalable assays with ... + Collaborate with automation engineers to implement the assays using automated systems for high-throughput screening. + Develop hit triage plans and mechanistic… more
    Bristol Myers Squibb (08/14/25)
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