• Senior CAD Engineer, Physical Design

    NVIDIA (Santa Clara, CA)
    …years industry experience. + Have an in-depth understanding of mosfet device behavior, CMOS layout, and VLSI design. + Experience working with standard cell design & ... layout. + Great interpersonal skills. + A passion for providing excellent support for end-users. NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most brilliant and talented people in the world working for us… more
    NVIDIA (07/29/25)
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  • Sr. Manager, Analog Mixed Signal IC Design

    Teledyne (Camarillo, CA)
    …designing Digital Analog Mixed Signal IR ROIC designs. + Strong background with CMOS semiconductor IC design including performing full custom analog IC layout. + ... Thorough understanding of deep sub-micron layout design practices such as parasitic RC delay, signal integrity, metal density rules, transistor, and capacitor matching. + Strong background with full custom circuit, block, and chip layout using Cadence Virtuoso… more
    Teledyne (07/29/25)
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  • Sr. CPU Architect, Project Kuiper

    Amazon (San Diego, CA)
    …to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: - Work closely with ... the system architects to define and architect world-class SoC and IP blocks, which meet power, area and performance targets. - Define compute architecture for wireless protocol stack and packet processing. - Develop performance model to evaluate the… more
    Amazon (07/23/25)
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  • LIS Sr Technician / Field Service Engineer

    CBRE (Sacramento, CA)
    …as contract research organizations (CROs) and contract manufacturing organizations ( CMOs ). Our comprehensive range of services includes laboratory consulting, real ... estate services, instrumentation repair and maintenance, full asset management, and more-covering the entire spectrum of life sciences facilities. With expertise across various life sciences categories, CBRE is a leader in managing highly-regulated spaces… more
    CBRE (07/22/25)
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  • Sr. ASIC Design Engineer, Blink/Ring ASIC Team

    Amazon (Sunnyvale, CA)
    …the latest in AI, video processing, low power communications and CMOS fabrication technology. Key job responsibilities -Define architecture specifications based on ... requirements from product teams -Create microarchitecture specifications suitable for being implemented by junior engineers -Evaluate 3rd party IP blocks -Estimate power, performance, and area for significant IPs early in design cycle -Execute on design… more
    Amazon (07/19/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …modeling and its usage in the ASIC flow. Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond. + Expertise in ... coding- TCL, Python. C++ is a plus. Familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc. + Strong communications skill and good standout colleague With competitive salaries and a generous benefits package, NVIDIA is widely considered to… more
    NVIDIA (07/19/25)
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  • Senior Reliability Engineer

    NVIDIA (Santa Clara, CA)
    …BGA and COWOS packaging technologies. + You are equipped with knowledge of CMOS devices physics, and familiar with reliability statistics, and models. + Familiar ... with industry standards (like JEDEC, IPC, AEC-Q100) + Proficient in reliability data analysis tool such as JMP, Weibull++ and/or Minitab + 8+ years of experience in IC reliability + BS or higher degree in Electrical Engineering, Physics, Material Sciences or… more
    NVIDIA (07/17/25)
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  • Analog Design & Layout Engineer

    University of Southern California (Los Angeles, CA)
    …layout creation, and design rule compliance across various process technologies (eg, CMOS , BiCMOS, III-V). + Academic and Research Engagement: + Assist in the ... delivery of tape out classes at USC by demonstrating layout techniques and troubleshooting common design issues. + Support funded research projects by providing design and layout expertise, including post-layout simulation, parasitic extraction, and layout… more
    University of Southern California (07/16/25)
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  • Senior SERDES Design Engineer, Project Kuiper

    Amazon (San Diego, CA)
    …. Integrate 112Gbps PAM-4 SERDES IP into complex SoCs in advanced CMOS nodes Basic Qualifications - Bachelor's degree in Electrical / Communications Engineering ... or related field - 7+ years experience in SERDES design - Experience with high-speed, low-power SERDES IP, especially the PHY layer Preferred Qualifications - Master's / PhD degree in Electrical / Communications Engineering or related field - 10+ years of… more
    Amazon (07/15/25)
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  • Principal Thermal Mechanical Photonic Designer

    NVIDIA (Santa Clara, CA)
    …outstanding products. Teams are dedicated to the architecture and design of CMOS and Silicon-Photonics high-speed chip interfaces (NVLink, IEEE, PCIE, USB, OIF) and ... other sophisticated photonic functions. Strong hands-on lab experience with silicon evaluation, debugging, characterization, and bring up. What you will be doing: + Work on Thermal and Structural design of Silicon Photonic designs + Run stress simulation in… more
    NVIDIA (07/13/25)
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