• Application Engineer Architect-Physical Design

    Cadence Design Systems, Inc. (San Jose, CA)
    …is highly desired + Experience with advanced nodes 5nm and below Keywords; Fusion Compiler , Design Compiler , Primetime, STA, HLS, Joules, RTL, PnR The annual ... salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note… more
    Cadence Design Systems, Inc. (09/27/25)
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  • Contract Hardware Engineer Mid.

    ManpowerGroup (San Jose, CA)
    …asynchronous boundaries. + Experience with synthesis tools like Synopsys Design Compiler or Fusion Compiler , and Verilog/SystemVerilog programming. **What's in ... it for me?** + Opportunity to work on cutting-edge ASIC design projects in a dynamic environment. + Collaborate with experienced professionals and enhance your technical expertise. + Engage in innovative methodologies and contribute to high-quality digital… more
    ManpowerGroup (09/25/25)
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  • Software Engineer- AI/ML, AWS Neuron Distributed…

    Amazon (Cupertino, CA)
    …The ML Distributed Training team works side by side with chip architects, compiler engineers and runtime engineers to create, build and tune distributed training ... build distributed training support into PyTorch and JAX using XLA, the Neuron compiler , and runtime stacks. You will optimize models to achieve peak performance and… more
    Amazon (09/24/25)
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  • Intern 2026: Quantum Computing Applications…

    IBM (San Jose, CA)
    …capabilities to enable advantage-scale experiments * Developing and studying compiler optimizations for quantum circuits targeting fault tolerant architectures ... experience * Experience with quantum algorithm design and analysis, quantum compiler or computer architecture, experimental realization of quantum algorithms, or… more
    IBM (09/22/25)
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  • Senior Layout Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    …the new process design challenges. You will have the chance to work on custom and compiler ram layouts with cut in edge process technology that would be used on all ... from the Crowd: + SRAM digital custom block design experience + SRAM compiler experience With competitive salaries and a generous benefits package, NVIDIA is widely… more
    NVIDIA (09/20/25)
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  • Software Development Engineer - AI/ML, AWS Neuron,…

    Amazon (Cupertino, CA)
    …and many more. The ML Apps team works side by side with compiler engineers and runtime engineers to create, build and tune distributed inference solutions ... building distributed inference support into Pytorch, Tensorflow using XLA and the Neuron compiler and runtime stacks. This role will help tune these models to ensure… more
    Amazon (09/19/25)
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  • CISCO Networking P4 Engineer

    Cisco (Milpitas, CA)
    …on network devices. + Build, optimize, and enhance the backend of the P4 compiler to use the full potential of networking hardware. + Tackle complex resource ... flawless integration of P4 programs with next-generation IC designs, providing compiler support during hardware development phases. + Participate in the design… more
    Cisco (09/18/25)
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  • Senior Staff Software Engineer, Quantization…

    Google (Sunnyvale, CA)
    …the machine learning (ML) performance team, in collaboration with the compiler , runtime, customer engineering, tooling, and customer teams, including Search, Vertex, ... + Create research-to-production roadmaps, driving innovation. Collaborate with the compiler , runtime, serving and post-training stack leads on cross-functional… more
    Google (09/18/25)
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  • Principal Engineer, VLSI Design Engineering

    SanDisk (Milpitas, CA)
    …circuits + Proficiency with following Digital design tools + Synthesis - Synopsys Design Compiler , Cadence Genus or Cadence RTL Compiler + Static Timing - ... Synopsys Primetime or Cadence Tempus + Place and Route - Synopsys ICC or Cadence Encounter or Innovus + Familiarity with revision control tool and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design… more
    SanDisk (09/11/25)
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  • Staff Engineer, VLSI Design Engineering(Logic…

    SanDisk (Milpitas, CA)
    …circuits + Proficiency with following Digital design tools + Synthesis - Synopsys Design Compiler , Cadence Genus or Cadence RTL Compiler + Static Timing - ... Synopsys Primetime or Cadence Tempus + Place and Route - Synopsys ICC or Cadence Encounter or Innovus + Familiarity with revision control tool and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design… more
    SanDisk (09/10/25)
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