• Senior Physical Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …the Cloud infrastructure. We are looking for a **Senior Physical Design Engineer ** to join the team. **Responsibilities** + Accountable for Design-for-Test ( DFT ... Design (PD) domain. + Facilitate coordination across cross-functional teams, including DFT , RTL/Design/IP, Static Timing Analysis (STA), CAD, Architecture, Power &… more
    Microsoft Corporation (08/08/25)
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  • Lead Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This Digital IC ... with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test ( DFT ), Place & Route and Static Timing Analysis (STA).You may get involved… more
    Cadence Design Systems, Inc. (07/18/25)
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  • Senior ASIC Design Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …Clocking. + Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. + Get involved in ... The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible...is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design… more
    NVIDIA (07/29/25)
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  • Principal Analog Engineer

    Microsoft Corporation (Mountain View, CA)
    …and augmented reality. We are looking for a ** ** **Principal Analog Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) ... Interface with architecture, physical design (PD), design for test ( DFT ), and other teams to optimize tradeoffs within the...QA and Release process, Integration of IPs in major CPU , GPU or AI accelerator SoC's and close interactions… more
    Microsoft Corporation (08/14/25)
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  • SOC RTL Design Engineer , Hardware Compute…

    Amazon (Sunnyvale, CA)
    …Clocking, Reset, Test & Debug. - Develop and implement methodologies for I/O, DFT , Debug, Clocking and Power Management. Basic Qualifications - BS degree or higher ... knowledge of in one or more areas such as CPU , DSP, or programmable accelerators - SoC bring-up and...high-volume SoCs in advanced design nodes - Experience with DFT tools for scan and BIST insertion - Experience… more
    Amazon (07/24/25)
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  • Sr SOC Physical Design Engineer , Hardware…

    Amazon (Sunnyvale, CA)
    …is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of ... hard. Have fun. Make history. As a Physical Design Engineer , you will: - Work with RTL/logic designers to...solving physical design challenges across various technologies such as CPU , DDR, PCIe, fabrics etc. - Experience in extraction… more
    Amazon (06/05/25)
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  • Principal Test Engineer (Hardware)

    Palo Alto Networks (Santa Clara, CA)
    …capabilities to build our next-generation network firewalls. As a senior test engineer , you will be responsible for building advanced test platforms for network ... covering structural and functional testing for PCBA and System level + Drive DfT (Design for Testability) and functional test coverage analyses from early Prototype… more
    Palo Alto Networks (07/05/25)
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  • Senior Manufacturing Test Development…

    Google (Sunnyvale, CA)
    …+ 10 years of experience with architecting manufacturing test solutions for CPU /GPU based products. + Experience in technical leadership, project management, and ... via reviews and dashboards; work closely with design engineering teams on DFT and to manage dependencies for test development. + Develop technical documentation… more
    Google (08/19/25)
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