• Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU , GPU and SOC designs. + Owning static timing analysis and convergence of ... experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, and timing… more
    NVIDIA (06/24/25)
    - Related Jobs

  • Zoom Chat Development Engineer

    Zoom (San Jose, CA)
    …for this position Responsibilities: + Develop and maintain XMPP IM servers; + Design the overall architecture of features in XMPP and communication protocol with ... the production logs from server, analyze the XMPP process logic to identify the root cause; + Analyze erl_crash.dump...in the new release and compare the metrics of CPU /scheduler/memory with those of previous release); + Improve the… more
    Zoom (05/18/25)
    - Related Jobs

  • Hardware Engineering/RTL Implementation

    Qualcomm (San Diego, CA)
    …+ Complex Digital Logic Design : Experience with designing complex digital logic blocks and sub systems ( CPU , GPU, DSP, Always on Systems, Digital ... eligible to receive a US Government security clearance **Role:** As a Design Engineer , you'll play a critical role in shaping cutting-edge digital designs. Your… more
    Qualcomm (07/12/25)
    - Related Jobs