• Senior System SW Engineer , System…

    Palo Alto Networks (Santa Clara, CA)
    …for next generation firewall products, identify performance bottlenecks and solutions, design and model protocol and sub-component offload solutions. In addition to ... high level design work, you will also do hands-on coding, including:...such as PCIe + Experience with IPC mechanisms and multi- CPU architectures + New hardware bring-up experience desired +… more
    Palo Alto Networks (09/19/25)
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  • Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …and ability to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the crowd: + ... plans for NVIDIA's next generation of high-performance IPs for CPU , GPU and SOC designs. + Owning static timing...(or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools,… more
    NVIDIA (09/23/25)
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  • Principal, Design Engineering

    Celestica (San Jose, CA)
    …California City: San Jose **General Overview** **Job Title:** Principal, Design Engineering **Functional Area:** Engineering (ENG) **Career Stream:** Engineering ... with the product life cycle development (phase/gate deliverables). The Principal Engineer , Software works in cross functional teams with other designers, customers,… more
    Celestica (08/08/25)
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