• Sr. Design Verification Manager, Annapurna…

    Amazon (Cupertino, CA)
    Description AWS Utility Computing (UC) provides product innovations that continue to set AWS's services and features apart in the industry. As a member of the UC ... quality and making the right trade-offs. Key job responsibilities - Overall verification manger, driving multiple teams to ensure correctness and quality of our… more
    Amazon (08/16/25)
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  • Senior Design Verification Engineer, HW…

    Amazon (Sunnyvale, CA)
    …have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience ... Description The team that built the innovative Silicon...of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of… more
    Amazon (08/10/25)
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  • Sr. Physical Design Verification Engineer,…

    Amazon (Cupertino, CA)
    Description Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create ... We're looking for an ASIC Physical Design Integration and Verification Engineer to join our backend team. The ideal...of the qualifications and skills listed in the job description , we encourage candidates to apply. If your career… more
    Amazon (07/30/25)
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  • Senior Design Verification Engineer, HW…

    Amazon (Sunnyvale, CA)
    …have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience ... Description The team that built the innovative Silicon...of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of… more
    Amazon (06/24/25)
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  • ASIC Engineer, Formal Verification

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal ... Verification to build IP and System On Chip (SoC)...collaboration with cross functional teams 15. Fluency in hardware description languages, such as SystemVerilog and SVA 16. Proficiency… more
    Meta (08/01/25)
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  • FPGA Verification Engineer, Kuiper Payload…

    Amazon (Sunnyvale, CA)
    Description Kuiper Production team FPGA Verification engineer. Creating & Maintaining verification environments and test suites for FPGA based subsystems. ... a groundbreaking new system with few legacy constraints. The FPGA verification engineer will work with design and systems teams to… more
    Amazon (07/05/25)
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  • Design Verification Engineer

    Arrow Electronics (Mountain View, CA)
    **Position:** Design Verification Engineer **Job Description :** Principal Accountabilities * Responsible for architecting Verification Environment for ASIC ... SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development * Develop complex… more
    Arrow Electronics (06/26/25)
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  • ASIC FPGA Design and Verification Engineer…

    The Boeing Company (Mountain View, CA)
    **Job Description ** At Boeing, we innovate and collaborate to make the world a better place. We're committed to fostering an environment for every teammate that's ... Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** (Experienced, Lead, or Senior) to join us as part of our… more
    The Boeing Company (07/26/25)
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  • UVM/ SystemVerilog Design Verification

    US Tech Solutions (Goleta, CA)
    **Job Description :** + The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as ... internal components and send data. **Responsibilities** + As a UVM/ SystemVerilog Design Verification Engineer, you will own functional verification for a custom… more
    US Tech Solutions (08/09/25)
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  • Design Verification Engineer

    Capgemini (Santa Clara, CA)
    …considering** Join a collaborative and forward-thinking team as a Design Verification Engineer, contributing to the validation of advanced System-on-Chip (SoC) ... high-quality silicon solutions. **Your role** + Architect and implement scalable verification environments using SystemVerilog and UVM for IP and SoC designs.… more
    Capgemini (07/09/25)
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