• Analog Design & Layout Engineer

    University of Southern California (Los Angeles, CA)
    … & Layout EngineerApply (https://usc.wd5.myworkdayjobs.com/ExternalUSCCareers/job/Marina-Del-Rey-CA/Analog- Design Layout- Engineer \_REQ20164538/apply) Viterbi ... between innovations and production. This role seeks a skilled engineer who excels in one or more of the...implementation. The successful candidate will work directly with MOSIS 2 .0 customers to help design and layout… more
    University of Southern California (07/16/25)
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  • Engineer / Principal Engineer

    Northrop Grumman (San Diego, CA)
    …making history. **Northrop Grumman Aeronautics Systems** is looking for an **Electrical Engineer ** to support the Circuit Design organization in **San Diego, ... CA** . As a member of the circuit design team, you will be responsible for circuit development..._Note: This position can be filled at the Electrical Engineer or Principal Electrical Engineer level._ **Basic**… more
    Northrop Grumman (07/08/25)
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  • RF Acoustic Wave Filter Design - Staff…

    Skyworks (Irvine, CA)
    …world communicates. Requisition ID: 75355 Position Summary This position is for a Staff Design Engineer of RF acoustic wave filters in Skyworks' headquater in ... + Strong circuit simulation skills utilizing Agilent ADS/Cadence and 2 .5/3D EM tools such as Momentum or HFSS +...Secondary Market:Los Angeles Job Segment: Electrical Engineering, Front End, Design Engineer , RF Engineer , … more
    Skyworks (07/06/25)
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  • Design Verification Engineer

    SpaceX (Irvine, CA)
    Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...in electrical engineering, computer science or computer engineering + 2 + years of experience with design verification… more
    SpaceX (06/21/25)
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  • Principal or Senior Principal Digital…

    Northrop Grumman (San Diego, CA)
    …of history, they're making history. Explore a career engineering what's possible as a Digital Design Engineer in San Diego, CA. **What You'll Get to Do:** Our ... the beach Southern California is famous. As a Digital Design Engineer at Northrop Grumman, you will...higher level MSSDEAS Salary Range: $118,000.00 - $177,000.00Salary Range 2 : $146,300.00 - $219,500.00 The above salary range represents… more
    Northrop Grumman (07/18/25)
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  • Lead Electrical Engineer - Underground…

    Black & Veatch (Walnut Creek, CA)
    …associated with this requisition: $103,194.00- $154,623.00 **Job Segment:** Construction, Design Engineer , Electrical Engineering, Engineer , Electrical, ... **Lead Electrical Engineer - Underground Transmission Line Design **...Lines + Renewables Integration + HVDC/FACTs This team is # 2 in ENR's Top 25 Design Firms… more
    Black & Veatch (08/08/25)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with ... state of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with...verification plans for each of the different core IP 2 . Define and track detailed test plans for the… more
    Meta (08/01/25)
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  • Package Design Engineer

    Meta (Menlo Park, CA)
    …create as part of a world-class engineering team. **Required Skills:** Package Design Engineer Responsibilities: 1. Drive chip-package-system co- design by ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its...structure, netlists, etc for High Performance Computing based on 2 .5D/3D package technology 2 . Hands on experience… more
    Meta (08/01/25)
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  • Package Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Package Design Engineer in the Advanced Technology Group (ATG). NVIDIA's GPUs and SOCs are the world leaders in power, ... this purpose, we are now seeking a passionate Package Design Engineer who is committed to making...Tcl desired) + Working knowledge of Cadence Allegro Packaging Design (APD) + Experience in 2 .5D packages… more
    NVIDIA (08/02/25)
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  • ASIC Engineer , Design Verification

    Meta (Menlo Park, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of a team working with the… more
    Meta (08/01/25)
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